Process for forming MOS device in integrated circuit structure u

Details Process for forming MOS device in integrated circuit structure u Process for forming MOS device in integrated circuit structure u

1997-07-09

1999-02-23

Quach, T. N.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438533, 438558, 438649, 438683, H01L 21336

Patent

active

058743421

ABSTRACT:
A process which is capable of forming shallow source/drain regions in a silicon substrate and a doped gate electrode by implantation of cobalt silicide contacts of uniform thickness previously formed on the substrate followed by diffusion of the dopant into the substrate to form the desired source/drain regions, and into the polysilicon gate electrode to provide the desired conductivity is described. The process comprises: first depositing a layer of cobalt over a polysilicon gate electrode and areas of a silicon substrate where source/drain regions will be formed; then forming at least one capping layer over the cobalt layer; then annealing the structure at a first temperature to form cobalt silicide; then removing the capping layer, as well as the unreacted cobalt and any cobalt reaction products other than cobalt silicide; then annealing the structure again at a higher temperature than the first anneal to form high temperature cobalt silicide; then implanting the cobalt silicide with one or more dopants suitable for forming source/drain regions in the silicon substrate and for increasing the conductivity of the polysilicon gate electrode; and then heating the structure sufficiently to cause the implanted dopant or dopants in the cobalt silicide to diffuse into the substrate to form the desired source/drain regions and into the polysilicon gate electrode to increase the conductivity thereof.

REFERENCES:
patent: 5356837 (1994-10-01), Geiss et al.
patent: 5529958 (1996-06-01), Yaoita
patent: 5567651 (1996-10-01), Berti et al.
Berti, Antonio C., et al., "A Manufacturable Process for the Formation of Self Aligned Cobalt Silicide in a Sub Micrometer CMOS Technology", 1992 Proceedings of VMIC Conference, Jun. 9-10, 1992, pp. 267-273.
Lui, R., et al., "Mechanisms for Process-Induced Leakage in Shallow Silicided Junctions", IEDM 86, Dec. 1986, pp. 58-61.
Shone, F.C., et al., "Formation of 0.1 .mu.m N.sup.30 /P and P.sub.+ /N Junctions by Doped Silicide Technology", IEDM 85, Dec. 1985, pp. 407-410.
Wang, Q. F., et al., "New CoSi.sub.2 Salicide Technology for 0.1 .mu.m Processes and Below", 1995 Symposium on VLSI Technology Digest of Technical Papers, Jun. 1995, pp. 17-18.
Yamazaki, Tatsuya, et al., "21 psec Switching 0.1 .mu.m-CMOS at Room Temperature Using High Performance Co Salicide Process", IEDM 93, Dec. 1993, pp. 906-908.

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