Process for forming metal interconnect stack for integrated...

Details Process for forming metal interconnect stack for integrated... Process for forming metal interconnect stack for integrated...

1999-10-26

2001-01-16

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S627000, C438S643000, C438S648000, C438S653000, C438S656000, C438S688000

Reexamination Certificate

active

06174798

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an improved metal interconnect for an integrated circuit structure. More particularly, this invention relates to a metal interconnect stack for an integrated circuit structure wherein a protective layer is added to the metal stack to inhibit reaction with an underlying tungsten-filled via or contact opening.
2. Description of the Related Art
Integrated circuit structures include metal interconnects to provide electrical connections between active and passive devices which form part of the integrated circuit structure. These generally horizontal metal interconnects, in turn, connect to generally vertical metal-filled vias or contact openings to provide both horizontal and vertical electrical access or connections throughout the integrated circuit structure.
As shown in prior art
FIGS. 1 and 2
, aluminum and copper, and their alloys, including aluminum/copper alloys, are at present, the materials of choice for the formation of a main metal interconnect layer
6
of a metal interconnect stack
1
. However, due to the interaction of aluminum and/or copper with other materials, such as A silicon substrate, a lower barrier layer
4
and an upper barrier layer
8
are usually provided, respectively, below and above main aluminum/copper metal interconnect layer
6
. Titanium nitride (TiN) is, at present, a popular material for use in formation of such barrier layers
4
and
8
.
It has been found that to maximize electron migration through main aluminum/copper metal interconnect layer
6
, main layer
6
should be composed of crystallographic grains with <
111
> orientation. To achieve such crystallographic orientation, it is very important that underlying TiN barrier layer
4
also has this <
111
> crystallographic orientation, since TiN barrier layer
4
, below main aluminum/copper metal interconnect layer
6
, acts as a seed layer during the CVD or PVD formation or deposition of main aluminum/copper metal layer
6
. However, to achieve a <
111
> orientation of underlying TiN barrier layer
4
, it has been found necessary to first provide a titanium metal layer
2
beneath TiN barrier layer
4
which when its surface had been cleaned to remove contaminates, in turn, acts as a seed layer for the formation of TiN barrier layer
4
with a <
111
> orientation.
Thus, conventional prior art metal interconnect stack
1
, as shown in
FIGS. 1 and 2
, comprises a titanium metal seed layer
2
having a cleaned surface thereon, lower TiN barrier layer
4
thereon having a <
111
> crystallographic orientation, a <
111
> aluminum/copper main metal interconnect layer
6
over TiN barrier layer
4
, and upper TiN barrier layer
8
formed over aluminum/copper main metal layer
6
.
The metal-filled vias or contact openings beneath the metal interconnect stack
1
provide vertical electrical connection either as metal-filled vias to an underlying metal interconnect stack or as metal-filled contact openings, for example, to underlying active or passive devices of the integrated circuit structure.
As shown in
FIGS. 1 and 2
, an insulation layer
14
, such as silicon oxide (SiO
2
)
14
is formed over an existing integrated circuit structure
12
(which may comprise a semiconductor substrate with active devices constructed therein, or may further comprise such structure as well as a lower insulation layer and a first metal interconnect stack already formed beneath insulation layer
14
). A via or interconnect opening
16
is formed in insulation layer
14
down to underlying integrated circuit structure
12
, and via
16
is filled with a conductive metal plug
20
.
Currently tungsten is the metal of choice used to form metal plug
20
to fill such vias or contact openings
16
, which in turn, make electrical contact with titanium layer
2
comprising the lowest layer of metal interconnect stack
1
.
However, as shown in prior art
FIGS. 1 and 2
, sometimes metal interconnect stack
1
and tungsten plug
20
in via or contact opening
16
are misaligned with respect to one another, resulting in exposure of a portion
22
of the upper surface of tungsten plug
20
(which surface should be completely covered by metal interconnect stack
1
).
Such misalignment results in an exposure of portion
22
of the upper surface of the tungsten plug
20
which can cause a corrosion problem which may, in turn, lead to failure of the integrated circuit structure. This is because the exposed titanium/tungsten interface, upon being contacted by either wet etchants used to pattern the metal interconnect stack or cleaning solutions used to clean the structure to remove etch residues after the etch step, can form a galvanic cell, with titanium layer
2
and tungsten plug
20
forming the electrodes and the etchant/cleaning solution acting as the electrolyte. This, in turn, can result in attack and erosion of tungsten plug
20
, as well as oxidation of titanium layer
2
.
Since some horizontal misalignment between metal interconnect stack
1
and tungsten plug
20
may occur, however infrequently, it would be of great benefit if the metal interconnect stack could be modified to inhibit such galvanic interaction between the tungsten plug in the via or contact opening and the titanium layer in the metal interconnect stack.
SUMMARY OF THE INVENTION
In accordance with the invention, a metal interconnect stack for an integrated circuit structure, comprising a main metal interconnect layer, an underlying TiN barrier layer and a titanium metal seed layer below the TiN barrier layer, and having protection against chemical interaction between the titanium metal seed layer and an underlying plug in a via, is formed by the steps of: providing an integrated circuit structure having an insulation layer formed thereon with one or more metal-filled vias or contact openings generally vertically formed therethrough to have an upper surface thereon; forming a lower barrier layer over the insulation layer and the upper surface of the metal in the one or more metal-filled vias; and subsequently forming the titanium seed layer over the lower barrier layer. This new lower barrier layer then separates the surface of the metal in the one or more vias from the titanium seed layer in the metal interconnect stack to inhibit galvanic action between the metal in the one or more vias and the titanium seed layer.
The TiN barrier layer directly below the main metal interconnect layer is then formed over the titanium seed layer, as a main TiN barrier layer, and the metal interconnect layer is then formed over this main TiN barrier layer. An optional upper TiN barrier layer may be formed over the main metal interconnect layer. Preferably, the main metal interconnect layer is provided with a <
111
> crystallographic orientation to enhance the electron migration of the main metal interconnect layer. To achieve this <
111
> orientation in the main metal interconnect layer, the main TiN barrier layer is preferably also provided with <
111
> crystallographic orientation to act as a seed layer for the main metal interconnect layer. The titanium metal seed layer then, in turn, functions as a seed layer for the main TiN barrier layer to assist in the formation of the main TiN barrier layer with the desired <
111
> orientation, so that the main TiN barrier layer will, in turn, act as a seed layer for the main metal interconnect layer.


REFERENCES:
patent: 5470790 (1995-11-01), Myers et al.
patent: 5594278 (1997-01-01), Uchiyama
patent: 5625231 (1997-04-01), Huang et al.
patent: 5675186 (1997-10-01), Shen et al.
patent: 5686760 (1997-11-01), Miyakawa
patent: 5780908 (1998-07-01), Sekiguchi et al.
patent: 5846871 (1998-12-01), Lee et al.
patent: 5892282 (1999-04-01), Hong et al.
patent: 6099701 (2000-08-01), Liu et al.
patent: 6110819 (2000-08-01), Colgan et al.

Affiliated with

Also associated with

Rating

Process for forming metal interconnect stack for integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for forming metal interconnect stack for integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for forming metal interconnect stack for integrated... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2484520