Process for forming high quality gate silicon dioxide layers...

Details Process for forming high quality gate silicon dioxide layers... Process for forming high quality gate silicon dioxide layers...

2000-02-18

2001-05-01

Le, Vu A. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S763000, C438S981000

Reexamination Certificate

active

06225163

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor device manufacturing methods and, in particular, to methods for forming gate silicon dioxide layers of multiple thicknesses.
2. Description of the Related Art
Typical Metal-Oxide-Semiconductor (MOS) semiconductor devices employ a gate silicon dioxide (SiO
2
) layer to separate a gate electrode from a semiconductor substrate. A variety of integrated circuits, including those with a mixture of analog MOS transistors and digital MOS transistors, require the formation of gate silicon dioxide layers of two different thicknesses.
A conventional method for forming gate silicon dioxide layers of two thicknesses is illustrated in
FIGS. 1-6
. The conventional method includes first supplying a semiconductor substrate
10
including electrical isolation region
12
, a high voltage active area
14
, and a low voltage active area
16
, as shown in FIG.
1
. An intermediate silicon dioxide layer
18
(e.g., 50 angstroms in thickness) is then grown on both the high and low voltage active areas. The resulting structure is illustrated in FIG.
2
. Next, as depicted in
FIG. 3
, a patterned photoresist layer
20
is formed covering a portion of the electrical isolation region
12
and a portion of the intermediate silicon dioxide layer
18
on the high voltage active area
14
, while leaving a portion of the intermediate silicon dioxide layer
18
on the low voltage active area
16
exposed. The exposed portion of the intermediate silicon dioxide layer
18
is subsequently removed from the low voltage active area
16
using the patterned photoresist layer
20
as an etch mask. In the circumstance where the exposed portion of the intermediate silicon dioxide layer
18
on the low voltage active area
16
is removed using an etching technique that also etches the electrical isolation region
12
, a step
22
can be created in the electrical isolation regions
12
, as illustrated in FIG.
4
. Following removal of the patterned photoresist layer
20
, a low voltage gate silicon dioxide layer
24
is grown on the low voltage active area
16
using a thermal oxidation technique. During the growth of low voltage gate silicon dioxide layer
24
, the intermediate silicon dioxide layer
18
that overlies the high voltage active area
14
is increased in thickness, thereby creating a high voltage gate silicon dioxide layer
26
overlying the high voltage active area
14
. Since the intermediate silicon dioxide layer
18
is being increased in thickness at the same time that the low voltage gate silicon dioxide layer
24
is being grown, the resulting high voltage gate silicon dioxide layer
26
is thicker than the low voltage gate silicon dioxide layer
24
. The resultant structure is shown in
FIG. 5. A
polysilicon layer (not shown) is then deposited and patterned to form high voltage patterned gate polysilicon layer
28
and low voltage patterned gate polysilicon layer
30
. The resultant structure is depicted in FIG.
6
.
There are several drawbacks associated with this conventional method. First, the quality (e.g., breakdown voltage and reliability) of the high voltage gate silicon dioxide layer
26
can be degraded due to contamination from contact with patterned photoresist layer
20
.
Second, since the high voltage gate silicon dioxide layer
26
has been formed using the process steps employed to grow both the intermediate silicon dioxide layer
18
and the low voltage gate silicon dioxide layer
24
, it can possess undesirable electrical characteristics. For example, if nitrogen is incorporated into the low voltage gate silicon dioxide layer
24
by employing a nitric oxide (NO) or nitrous oxide (N
2
O) ambient during its growth, the high voltage gate silicon dioxide layer
26
will also face some degree of nitrogen incorporation. If the high voltage gate silicon dioxide layer
26
is used as a portion of an analog transistor, nitrogen incorporation can produce poor analog electrical characteristics. For example, unbalanced (i.e., unmatched) threshold voltages (V
T
) between multiple analog transistors may result due to increased levels of trapping in the high voltage gate silicon dioxide layer
26
.
Third, thickness control of the high voltage gate silicon dioxide layer
26
can be difficult since it is formed using two growth steps: namely, the intermediate silicon dioxide layer growth step and the low voltage silicon dioxide layer growth step.
Fourth, the conventional methods cannot be easily extended to the formation of gate silicon dioxide layers of more than two thicknesses.
Still needed in the field, therefore, is a process for manufacturing high quality multiple thickness gate silicon dioxide layers. The process should (i) not include steps wherein a gate silicon dioxide layer is in direct contact with a photoresist layer; (ii) provide for thickness control by forming each of the gate silicon dioxide layers in one step; (iii) provide for high and low voltage gate silicon dioxide layers to be formed using independent growth steps; and (iv) be easily extendable to multiple gate silicon dioxide layers of more than two thicknesses.
SUMMARY OF THE INVENTION
The present invention provides a process for forming high quality gate silicon dioxide layers of multiple thicknesses. The process does not include steps where a gate silicon dioxide layer is in direct contact with a photoresist layer. The process according to the present invention provides for improved control of the thickness and electrical characteristics of the gate silicon dioxide layers by forming each of multiple gate silicon dioxide layers in single independent steps. Thus, in a case of dual thickness gate silicon dioxide layers, the formation of a first gate silicon dioxide layer and a second gate silicon dioxide layer is accomplished by two separate steps. Such a process can be easily extendable to multiple gate silicon dioxide layers of more than two thicknesses.
Processes according to the present invention include the steps of first providing a semiconductor substrate (e.g., a silicon wafer) with at least a first active area, a second active area and an electrical isolation region separating the first and second active areas, followed by the formation of a first gate silicon dioxide layer of a predetermined thickness on the first and second active areas. A first silicon layer (e.g., a polysilicon or amorphous silicon layer) is then deposited on the first gate silicon dioxide layer and the electrical isolation region. The first silicon layer is subsequently patterned to form a patterned first silicon layer, as well as to expose a portion of the first gate silicon dioxide layer that was formed on the second active area. Next, the exposed portion of the first gate silicon dioxide layer is removed. A second gate silicon dioxide layer of another predetermined thickness is then formed on the second active area. A second silicon layer (e.g., a polysilicon or amorphous silicon layer) is subsequently deposited on the second gate silicon dioxide layer and overlying the patterned first silicon layer. Finally, the second silicon layer is patterned to form a patterned second silicon layer.


REFERENCES:
patent: 6048800 (2000-04-01), Nagashima et al.
patent: 6110842 (2000-08-01), Okuno et al.
patent: 6124171 (2000-09-01), Arghavani et al.
patent: 6130132 (2000-10-01), Hsich et al.
patent: 6147008 (2000-11-01), Chwa et al.
patent: 6150220 (2000-11-01), Huh et al.
patent: 6153469 (2000-11-01), Yun et al.
patent: 6157058 (2000-12-01), Ogura

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