Process for forming gate oxides possessing different thicknesses

Details Process for forming gate oxides possessing different thicknesses Process for forming gate oxides possessing different thicknesses

1997-05-09

1999-06-29

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438197, 438981, H01L 218234

Patent

active

059181168

ABSTRACT:
Gate oxides having different thicknesses are grown on a semiconductor layer by the process which comprises forming a semiconductor layer on a substrate, growing an oxide layer on the semiconductor layer, exposing a selected area of the oxide layer, amorphizing the semiconductor layer underlying the exposed oxide layer, removing the oxide layer to expose the semiconductor layer having both amorphized and non-amorphized regions and growing gate oxide on the amorphized and non-amorphized regions of the semiconductor layer. Gate oxide grown on the amorphized regions will be thicker than gate oxide grown on the non-amorphized regions.
The process of the invention obviates the need for special integrated circuit manufacturing design modifications and can be utilized to fabricate a wide variety of devices, in particular, MOS-type devices.

REFERENCES:
patent: 3966501 (1976-06-01), Nomura et al.
patent: 4170492 (1979-10-01), Bartlett et al.
patent: 4651406 (1987-03-01), Shimizu et al.
patent: 4728619 (1988-03-01), Pfiester et al.
patent: 4743563 (1988-05-01), Pfiester et al.
patent: 4748134 (1988-05-01), Holland et al.
patent: 4912062 (1990-03-01), Verma
patent: 4920076 (1990-04-01), Holland et al.
patent: 4957873 (1990-09-01), Ojha et al.
patent: 5021354 (1991-06-01), Pfiester
patent: 5043292 (1991-08-01), Aronowitz et al.
patent: 5045486 (1991-09-01), Chittipeddi et al.
patent: 5057449 (1991-10-01), Lowrey et al.
patent: 5244843 (1993-09-01), Chau et al.
patent: 5266849 (1993-11-01), Kitahara et al.
patent: 5296386 (1994-03-01), Aronowitz
patent: 5304872 (1994-04-01), Avraham et al.
patent: 5316981 (1994-05-01), Gardner et al.
patent: 5328866 (1994-07-01), Chang et al.
patent: 5330920 (1994-07-01), Soleimani
patent: 5358894 (1994-10-01), Fazan et al.
patent: 5372952 (1994-12-01), Aronowitz et al.
patent: 5432114 (1995-07-01), O
patent: 5480828 (1996-01-01), Hsu et al.
patent: 5576226 (1996-11-01), Hwang
Translation of DDR 242905 (Rost et al.).
O. W. Holland et al., Appl. Phys. Lett. 51(7) (1987) 520 "Novel Oxidation process in Ge.sup.+ -implanted Si . . . ".
S. Wolf + R. N. Tauber "Silicon Proc. for VLSI Era" vol. I, pp. 198-201, 290-291, 294-308, 323, 327 (1986).
S. Wolf, "Silicon Proc. for the VLSI Era" vol. II, pp. 27, 373, 382, (1992).
P. J. Wright, et al., "IEEE Trans. on Electron Dev.", 36, 5 (1989)879 "F in SiO.sub.2 Gate Dielectrics" (Abstract).
N. Kasai, et al., "IEEE Trans. on Electron Dev." (Abstract) 37,6 (1990) 1426 ". . . F incorporated n-MOSFETS".
J.C. Hsieh, et al., "IEEE Electron Dev. Lett", 14, 5 (1993)222 ". . . BF.sub.2 2 or B implanted Polysi Gate W.+ W/O POCL3 . . . ".
G. Greeuw et al., "Solid St. Electronics" 26,3(1983)241 "Donor Generation in Mono-Si by Halogen Implantation".
S. Wolf, "Silicon Processing for the VLSi Era", vol. II, pp. 385-389, Jun. 1990.
Translation of JP 6-53492, Feb. 1994.
EPO Search Report EP 95308353.2.
D.J. Roth et al., "Silicon Interstitial Absorption During Thermal Oxidation at 900.degree. C By Extended Defects Formed Via Silicon Implantation", Applied Physics Letters, vol. 62, No. 20, May 17, 1993, pp. 2498-2500.
D.B. Slater, Jr. et al., "Fabrication of High Quality Capacitors By Impurity Enhanced Oxidation", Journal of the Electrochemical Society, vol. 135, No. 12, Dec. 1988, pp. 3098-3103.
D.B. Slater, Jr. et al., "Low-Voltage Coefficient Capacitors for VLSI Processors", IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989, pp. 165-173.
X.-W. Wang et al., "Pre-Oxidation Fluorine Implantation into Si", Journal of the Electrochemical Society, vol. 139, No. 1, Jan. 1, 1992, pp. 238-241.
David B. Slater Jr. and John J. Paulos, Low Voltage Coefficient Capacitors for VLSI Processes, IEEE Journal Solid State Circuits, vol. 24, No. 1, pp. 165-173, Feb. 1989.
David B. Slater Jr. and John J. Paulos, Fabrication of High Quality Capacitors by Impurtity Enhanced Oxidation, Journal of the Electrochemical Society, vol. 135, No. 12, pp. 3098-3103, Dec. 1988.

Affiliated with

Also associated with

Rating

Process for forming gate oxides possessing different thicknesses does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for forming gate oxides possessing different thicknesses, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for forming gate oxides possessing different thicknesses will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1386376