Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-06-28
2003-05-06
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S132000, C438S612000, C438S333000, C438S467000
Reexamination Certificate
active
06559042
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the fabrication of integrated circuits and more particularly, to the fabrication of an integrated circuit employing fusible links.
Integrated circuits are now transitioning from aluminum to copper metal interconnects as device generation goes beyond the 0.25 &mgr;m design rules. Aluminum metal is limited for these design rules due to its inability to reliably carry current in smaller sized circuit lines. Copper has lower resistivity than aluminum so it can carry more current in smaller areas, thus enabling faster and denser chips with increased computing power. Along with the transition from aluminum to copper is the improvement upon the dielectric insulating layers. Silicon dioxide has been traditionally used as the primary material for insulators and has a dielectric constant of about 3.9. New insulating materials such as low k dielectrics have been proposed, which lower interconnect capacitance and crosstalk noise to enhance circuit performance. These low k dielectrics typically comprise polymers and have dielectric constants less than about 3.0 Some examples of low k dielectrics include polyimide, fluorocarbons, parylene, hydrogen silsequioxanes, benzocyclobutenes and the like.
Fabrication of integrated circuits using copper and low k dielectrics present new challenges and problems for the semiconductor manufacturer. One change that has resulted is the implementation of a Damascene process to integrate copper into the circuit. Using the Damascene process, openings defining the wiring patterns are provided in the dielectric layer, extending from one surface of the dielectric layer to the other surface of the dielectric layer. These wiring patterns are then filled with a metallization metal using a filling technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or a combination of methods. This process may include planarization of the metal on the surface of the dielectric removing excess metallization with a method such as chemical mechanical polishing.
The Damascene process uses most of the traditional structure but differs in the way the structure is built. Instead of etching as pattern in a metal film and surrounding it with dielectric material, a damascene process etches a pattern in a dielectric film, then fills the pattern with copper. An advantage of the Damascene process is that the metal etch is replaced with a simpler dielectric etch as the critical step that defines the width and spacing of the interconnect lines. In a single Damascene process, vias or openings are additionally provided in the dielectric layer and filled with metallization to provide electrical contact between layers of wiring levels. In the dual Damascene process, the via openings and the wiring pattern openings are both provided in the dielectric layer before filling with metallization.
Integrated circuits include a large number of semiconductor devices typically fabricated on a silicon substrate. To achieve the desired functionality, a plurality of conductors are usually provided to electrically couple selected devices together. In some integrated circuits, conductive links are coupled to fuses, which may be cut or blown after fabrication. The links are typically cut or blown using lasers or by an electrical pulse. In a dynamic random access memory (DRAM) circuit, fusible links may be used to replace failing or defective memory array elements with redundant array elements. To this end, additional segments of memory arrays are provided on the integrated circuit as replacements for the defective or failing segments. In logic circuits, fuses may be used to select or modify circuit performance or functions. Fusible links comprise metal lines that can be explosively fused open by application of laser energy or an electrical pulse which causes a portion of the link material to vaporize and a portion to melt. Typically, the fusible link is thin and composed of aluminum or polysilicon. However, the integration of copper and low k materials presents new problems for the manufacturer of integrated circuits employing fusible links.
Fusible links are generally formed as part of one of the metallization layers during fabrication of the integrated circuit. Typically a lower level, such as polysilicon, is used. This level would for example, contain the wordlines of a DRAM array. Prior to causing the link to open by application of laser energy, the interlevel dielectric layers above the fusible link are sometimes removed entirely and replaced by a thinner protective layer. The removed portions of insulating layer provide a short uniform path for the laser and confine the resultant debris. In other cases, the thick dielectric layers are etched down to a predetermined thickness above the link. The laser energy required to blow the fuse is proportional to the thickness of the dielectric material above the fuse.
The laser access window is commonly opened in a final etch step after the uppermost metallization level has been patterned and a final passivation layer has been deposited. The passivation layer is patterned to form access openings to bonding pads in the uppermost metallization level and, simultaneously form access openings to the fuses. At the bonding pads, the etch must penetrate the passivation layer and an antireflective coating (ARC) on the pad. However, the fuse openings must pass through not only the passivation layer, but the additional thickness of subjacent insulative layers. Even though etch rate selectivities favorable for etching insulative material over metallization are used, it is difficult to etch the entire fuse opening simultaneously with the bonding pad openings without either degrading the bonding pad by over-etching or leaving too much or too little or no insulator over the fuses. In current technology, the ARC over the bonding pads must also be removed by the passivation layer patterning step. This requires significant over-etching of the bonding pad and often results in excessive or total removal of insulative layer over the fuses. The total removal of the insulative layer is especially problematic since it exposes the fuses to atmospheric moisture and corrosion. As a result, the fuses are subject to oxidation and corrosion.
The integration of copper and low k dielectrics further complicates formation of fusible links. Some of the low k dielectrics have a relatively high oxygen diffusivity constant compared to traditional dielectrics, such as silicon dioxide. The build-up of copper oxide is detrimental to device performance. Higher contact resistance results from oxidation and corrosion, which impedes the flow of current through the integrated circuit. Thus, it is important to design a process that minimizes and/or eliminates oxidation of the copper. The process must also take into consideration that the choice of low k dielectric material will impact oxidation of the copper due to its oxygen diffusivity. Thus the process should minimize and/or eliminate exposure of the low k dielectric to the atmosphere.
Therefore, there is a need for an improved fusible link design and fabrication process that can be integrated with the newer materials being used in semiconductor manufacturing.
SUMMARY OF THE INVENTION
A process for forming a fusible link in an integrated circuit. The process includes
forming a second dielectric layer on a planarized surface of an underlying metal interconnect and first dielectric layer. An oxide layer is deposited onto the second dielectric layer at a thickness effective to prevent cracking of the oxide layer during a laser fuse process. The oxide layer is patterned to form a via extending through the second dielectric layer to the underlying metal interconnect. The via is filled with a conductive metal. A final metal layer is deposited onto the substrate and patterned to form a fusible link, a bonding pad area and a desired wiring pattern. A passivation layer is deposited and patterned to simultaneously open the bonding pad area and a portion of the
Barth Hans-Joachim
Burrell Lloyd G.
Friese Gerald R.
Stetter Michael
Blecker Ira
Cantor & Colburn LLP
Cothorn Judith A.
International Business Machines - Corporation
Zarabian Amir
LandOfFree
Process for forming fusible links does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for forming fusible links, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for forming fusible links will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3027081