Process for forming dual metal gate structures

Details Process for forming dual metal gate structures Process for forming dual metal gate structures

2005-06-07

2005-06-07

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S200000, C438S216000, C438S218000, C438S233000

Reexamination Certificate

active

06902969

ABSTRACT:
A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with a gate dielectric/etch stop layer stack. The N channel gate stack and the P channel gate stack are etched by a dry etch. Either the gate dielectric or etch stop can be in contact with the substrate. The etch stop layer prevents the dry etch of the first and second metal layers from etching through the gate dielectric and gouging the underlying substrate.

REFERENCES:
patent: 6492217 (2002-12-01), Bai et al.
patent: 2002/0151125 (2002-10-01), Kim et al.
Adetutu, Olubunmi O., Process for Forming Dual Metal Gate Structures, U.S. Appl. No. 10/410,043, filed Apr. 9, 2003.

Affiliated with

Also associated with

Rating

Process for forming dual metal gate structures does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for forming dual metal gate structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for forming dual metal gate structures will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3496370