Process for forming dual metal gate structures

Details Process for forming dual metal gate structures Process for forming dual metal gate structures

2003-04-09

2004-09-14

Lee, Hsien Ming (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having junction gate

C438S216000, C438S233000, C438S199000

Reexamination Certificate

active

06790719

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to making integrated circuits using metal gates, and more particularly, to making integrated circuits using metal gates of differing structures.
RELATED ART
As semiconductor devices continue to scale down in geometry, the conventional polysilicon gate is becoming inadequate. One problem is relatively high resistivity and another is depletion of dopants in the polysilicon gate in the location near the interface between the polysilicon gate and gate dielectric. To overcome these deficiencies of polysilicon, metal gates are being pursued as an alternative. For desired functioning of the P channel transistors and the N channel transistors, the work functions of the metals used for the N channel and P channel transistors should be different. Thus, two different kinds of metals may be used as the metal directly on the gate dielectric. Metals that are effective for this generally are not easily deposited or etched. Two metals that have been found to be effective are titanium nitride for the P channel transistors and tantalum silicon nitride for N channel transistors. The etchants typically used for these materials, however, are not sufficiently selective to the gate dielectric and silicon substrate thus gouging may occur in the silicon substrate. This arises because in the P channel active regions, the titanium nitride is under the tantalum silicon nitride. The etch process that is used for the removal of the tantalum silicon nitride over the P channel active regions is necessary to expose the titanium nitride for subsequent etching also exposes the gate dielectric in the N channel active regions. As a consequence, the etch of the titanium nitride is also applied to the exposed gate dielectric in the N channel active regions where source/drains are to be formed. This etch of the titanium nitride may have the adverse effect of also removing the exposed gate dielectric and gouging the underlying silicon where the source/drains are to be formed.
Thus, there is a need for a process for forming dual gate transistors that solves the issues described above.


REFERENCES:
patent: 6171959 (2001-01-01), Nagabushnam
patent: 6214681 (2001-04-01), Yu
patent: 6417104 (2002-07-01), Hu
patent: 6444512 (2002-09-01), Madhukar
patent: 6492217 (2002-12-01), Bai et al.
patent: 2002/0151125 (2002-10-01), Kim et al.

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