Process for forming DRAM cell

Details Process for forming DRAM cell Process for forming DRAM cell

1997-07-07

2003-04-15

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S255000

Reexamination Certificate

active

06548346

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the formation of capacitors for integrated circuit memories and particularly to methods of forming high capacitance structures in a high production manufacturing environment.
2. Description of the Related Art
In dynamic random access memories (DRAMs), information is typically stored by selectively charging or discharging each capacitor of an array of capacitors formed on the surface of a semiconductor substrate. Most often, a single bit of binary information is stored at each capacitor by associating a discharged capacitor state with a logical zero and a charged capacitor state with a logical one. The surface area of the electrodes of the memory capacitors determines the amount of charge that can be stored on each of the capacitors for a given operating voltage, for the electrode separation that can reliably be manufactured, and for the dielectric constant of the capacitor dielectric used between the electrodes of the charge storage capacitor. Read and write operations are performed in the memory by selectively coupling the charge storage capacitor to a bit line to either transfer charge to or from the charge storage capacitor. The selective coupling of the charge storage capacitor to the bit line is typically accomplished using a transfer field effect transistor (FET). The bit line contact is typically made to one of the source/drain electrodes of the transfer FET and the charge storage capacitor is typically formed in contact with the other of the source/drain electrodes of the transfer FET. Word line signals are supplied to the gate of the FET to connect one electrode of the charge storage capacitor through the transfer FET to the bit line contact facilitating the transfer of charge between the charge storage capacitor and the bit line.
There is a continuing trend toward increasing the storage density of integrated circuit memories to provide increased quantities of data storage on a single chip. Higher density memories provide storage that is generally more compact and is often cheaper on a per bit basis than an equivalent amount of storage provided on plural chips. It has generally been possible to provide these higher levels of storage at equivalent or improved levels of performance as compared to the earlier, less dense memory chips. Historically, the density of integrated circuit devices has been increased in part by decreasing the size of structures such as wiring lines and transistor gates as well as by decreasing the separation between the structures that make up the integrated circuit device. Reducing the size of circuit structures is generally referred to as decreasing the “design rules” used for the manufacture of the integrated circuit device.
Applying reduced design rules to a DRAM reduces the substrate surface area that can be devoted to the charge storage capacitor of the DRAM. Thus, applying reduced design rules to conventional planar capacitor designs reduces the amount of charge (i.e., capacitance) that can be stored on the charge storage capacitor. Reducing the amount of charge on the capacitor leads to a variety of problems, including the potential loss of data due to greater susceptibility to decay mechanisms and to charge leakage. This greater susceptibility to charge loss may cause the DRAM to require more frequent refresh cycles, which are undesirable since the memory may be unavailable for data storage and readout transactions during refresh activities. In addition, reduced levels of charge storage might require more sophisticated data readout schemes or more sensitive charge sensing amplifiers. Thus, modem DRAMs require increased levels of capacitance in reduced substrate area DRAM cells. To this end, a variety of very complex capacitor structures having three dimensional charge storage surfaces have been proposed. In general, these complex capacitor structures are difficult to manufacture. This is particularly true when the requirements are taken into account for forming such capacitor structures in a high throughput manufacturing environment in a manner compatible with high yields. It is accordingly an object of the present invention to provide a capacitor structure that is more compatible with a high volume manufacturing environment.
SUMMARY OF THE PREFERRED EMBODIMENTS
According to one aspect, the present invention forms a DRAM including charge storage capacitors on a substrate having charge storage capacitor access circuitry such as transfer transistors formed thereon. The method of forming a DRAM includes forming a transfer transistor including a gate electrode and first and second source/drain regions on a substrate and opening a contact via to expose at least a portion of the first source/drain region. A first polysilicon layer is deposited over the contact via and then a sacrificial layer is provided over the first polysilicon layer which is patterned to form a sacrificial structure having sidewalls. Spacers are formed on the sidewalls of the sacrificial structure and the sacrificial structure is removed. In a first etching process, the first polysilicon layer is etched using the spacers as a mask in an anisotropic etching process to form a vertically extending structure electrically connected to the first source/drain region.


REFERENCES:
patent: 5330614 (1994-07-01), Ahn
patent: 5358888 (1994-10-01), Ahn et al.
patent: 5447878 (1995-09-01), Park et al.

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