Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-07-03
2003-11-25
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06653182
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior French Patent Application No. 0008686, filed Jul. 4, 2000, the disclosure of which is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the field of integrated circuits and more particularly to forming insulative regions for electrically isolating bipolar and biCMOS transistors, especially transistors for radio frequency applications.
2. Description of Related Art
Deep insulative trenches formed all around a bipolar transistor significantly reduce the collector/substrate capacitance in radio frequency applications. The maximum frequency of oscillation of the transistors is inversely proportional to the square root of the collector/substrate capacitance.
During the fabrication of MOS and bipolar transistors, deep trenches are excavated into the substrate of the integrated circuit. These deep trenches are often filled with an insulative material that flows well into the trench. The flow of insulative material into the trench reduces the problems of mechanical stresses, because the high temperature heat treatments to fabricate the transistors have already been carried out.
The use of deep insulative trenches in the substrate although useful is not without it shortcomings. One shortcoming is the formation of insulative trenches outside the contact areas, in particular outside the base contact area. The formation of contact areas outside the base contact area increases the length of the insulative trench. This results in an increased collector/substrate capacitance and a larger overall size of the transistor, and therefore a lower level of integration.
Accordingly a need exists for a method to fabricate a circuit with insulative trenches that overcomes the prior art problems and shortcomings of reducing collector/substrate capacitances while minimizing the size of the overall transistor.
Mixed bipolar and MOS transistors (biCMOS technology) are useful in many different applications. The formation of insulative trenches in biCMOS technology is known. For example in bipolar transistors, the surfaces are isolated from other components by LOCOS insulative regions, as is well known to the persons of average skill in the art LOCOS insulative regions also isolate the extrinsic collector from the base region.
On the other hand, MOS transistors are insulated on the surface by shallow insulative trenches. Forming the shallow insulative regions requires heat treatment at very high temperatures. In particular the very high temperatures are used to soften the corners of the trenches. This process of using very high temperatures to soften corners prevent dislocations in the silicon of the active area, which would cause a leakage current. The combination of trench isolation techniques used in bipolar and MOS transistors presents a problem.
Accordingly a need exists for a method to permit the fabrication of mixed bipolar and MOS transistors with shallow insulative trench.
SUMMARY OF THE INVENTION
The present invention provides a method to form deep insulative trenches around bipolar transistors at the beginning of the process, i.e. before the transistors are fabricated, in order to be able to reduce the distance between the deep insulative trenches and the active area of the transistors and thereby reduce the collector/substrate capacitance, while allowing a higher level of integration because of a smaller overall size.
The present invention forms insulative regions that are totally compatible with the biCMOS technology, i.e. for the simultaneous fabrication of bipolar transistors and MOS transistors. In this regard, the present invention enables mixed insulative regions to be made, i.e. regions made up of deep trenches surmounted by shallow trenches also made at the beginning of the process.
The invention therefore proposes a method of forming an insulative region within a substrate of an integrated circuit including transistors.
In accordance with one general feature of the invention, the method includes, before fabricating the transistors, a phase of forming a deep insulative trench in the substrate followed by a phase of making a shallow insulative trench in the substrate which is nosier the surface and extends the deep trench. The phase of forming the deep trench (or “surface”, to use a somewhat strained term to contrast with “deep”) includes coating the inside walls of the trench with an initial oxide layer, for example a silicon dioxide layer, obtained by rapid thermal oxidation and filling the trench with silicon inside an envelope formed from an insulative material for example a layer of tetraethyl orthosilicate (TEOS) oxide. The phase of forming the shallow trench also includes coating the inside walls of the trench with an initial oxide layer obtained by rapid thermal oxidation and filling the trench with an insulative material.
Rapid thermal oxidation (RTO) minimizes the thermal balance and consequently prevents layers buried in the substrate rising by diffusion.
Another advantage of the method according to the invention is the high mechanical strength of the structure obtained. Rapid thermal oxidation softens the corners of the trenches, which would otherwise constitute areas of stress concentration leading to the onset of dislocations.
Moreover, as explained in more detail later, rapid thermal oxidation avoids the formation of a cup at the edge of the shallow trench during successive etching operations. These cups lead to the formation of a spurious transistor at the corner of the active area, and this leads to a lack of homogeneity of the threshold voltage of the transistor in the active area, the voltage being higher at the center than at the edge, and this increases the leakage currents of the transistor as a whole.
Filling the deep trench with a semiconductor material similar to that of the substrate. Semiconductor material such as silicon or polycrystalline has been shown to work advantageously well for the present invention and minimizes the problems of expansion during subsequent heat treatment at high temperatures to fabricate the transistors.
Rapid thermal oxidation is advantageously carried out for not more than approximately 150 seconds and at a temperature of not more than 1,150° C.
In one embodiment of the invention, the phase of forming the deep trench includes:
a) etching the substrate to form a deep cavity in the substrate;
b) coating the inside walls of the cavity with the initial thermal oxide layer;
c) depositing a second insulative layer on the structure obtained in step b);
d) depositing a silicon layer on the structure obtained in step c);
e) mechanically/chemically polishing the silicon layer as far as the second oxide layer;
f) etching the upper part of the silicon present in the trench as far as the level of the upper surface of the substrate; and
g) partially etching the second insulative layer to an etching depth substantially equal to the depth of the shallow trench.
The phase of forming the shallow trench advantageously includes:
a) etching the upper part of the substrate to form a shallow cavity whose bottom is substantially at the same level as the boundary of the second insulative layer in the underlying deep trench;
b) de-oxidation of the inside walls of the cavity;
c) coating the inside walls of the cavity with the initial thermal oxide layer;
d) filling the coated cavity with the insulative material; and
e) mechanically/chemically polishing the insulative material.
The invention also provides an integrated circuit including insulative regions for separating transistors within a semiconductor substrate.
According to one general feature of the invention, at least one insulative region includes a deep insulative trench opening into a shallow insulative trench filled with an insulative material, the deep trench containing silicon separated from the inside walls of the trench by an insulative material.
REFERENCES:
patent: 5358891 (1994-10-01), Tsang et al.
Baudry Hélène
Leverd François
Marty Michel
Fleit Kain Gibbons Gutman Bongini & Bianco P.L.
Gibbons Jon A.
Hoang Quol
Jorgenson Lisa K.
Nelms David
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