Process for forming CMOS transistors and MOS transistors of...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S210000, C438S719000

Reexamination Certificate

active

07005336

ABSTRACT:
A process is disclosed for forming, on a common semiconductor substrate, CMOS transistors and vertical or lateral MOS transistors on at least first and second portions, respectively, of the substrate. A first dielectric layer is formed on the substrate. A first semiconductor material layer is then formed on the first dielectric layer, in the first portion. A stack structure comprising a second dielectric layer, second semiconductor layer, and low-resistance layer is then formed over the substrate. First ports are defined in the second semiconductor layer and the low-resistance layer to provide gate regions of the vertical or lateral MOS transistors. The second semiconductor layer and the low-resistance layer are then removed from the first portion of the substrate by using the second dielectric layer as a screen. Second ports in the second dielectric layer and the second semiconductor layer are then defined to provide gate regions for the CMOS transistors. The gate region of the vertical or lateral transistors is then covered with a protective layer. A low-resistance layer is then formed on the gate regions of the CMOS transistors.

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Tsui, et al., “Integration of Power LDMOS into a Low-Voltage 0.5 um BiCMOS Technology”, Electron Devices Meeting, Technical Digest, International San Francisco, CA, Dec. 13-16, 1992, IEEE, US, pps. 27-30; XP010106441; ISBN: 0-7803-081704.
European Search Report, EP 02425807, dated Oct. 9, 2003.

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