Process for forming capacitor over bit line memory cell

Details Process for forming capacitor over bit line memory cell Process for forming capacitor over bit line memory cell

1997-12-24

2000-05-09

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438672, H01L 218242

Patent

active

060603518

ABSTRACT:
A stacked capacitor memory cell and method for its fabrication including providing a layer of insulation glass over word lines on a silicon semiconductor substrate; self-aligning contact holes at the storage nodes and bit line contact location; providing a blanket layer of polysilicon, then silicide, and then an insulating cap; removing a portion of the insulating cap, silicide and polysilicon to form polysilicon plugs having outward surfaces at an elevation below the surface of the insulating glass, thus forming the bit line, a bit line contact and isolating the storage nodes; and providing a stacked capacitor on top of the bit line and in electrical communication with the storage node contact location through the plugs formed simultaneously with the bit line and bit line contact.

REFERENCES:
patent: 5296400 (1994-03-01), Park et al.
patent: 5401681 (1995-03-01), Dennison
patent: 5721154 (1998-02-01), Jeng
patent: 5789304 (1998-08-01), Fischer et al.
patent: 5792687 (1998-08-01), Jeng et al.

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