Process for forming an integrated circuit comprising non-volatil

Details Process for forming an integrated circuit comprising non-volatil Process for forming an integrated circuit comprising non-volatil

1996-06-20

1999-12-21

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438201, 438261, H01L 218247

Patent

active

060048476

ABSTRACT:
A process for forming an integrated circuit includes at least one matrix of non-volatile memory cells having an intermediate dielectric multilayer including at least a lower dielectric material layer and an upper silicon oxide layer. The integrated circuit includes at least one transistor simultaneously formed in zones peripheral to the matrix and having a gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower dielectric material layer, the process includes removal of said layers from the peripheral zones of the matrix; deposition of said upper silicon oxide layer over the memory cells, and over the substrate in the areas of the peripheral transistors; and formation of a first silicon oxide layer at least in the areas of the peripheral transistors. A second transistor type can be formed having a gate dielectric of a second thickness, thinner than said first thickness, in successive steps.

REFERENCES:
patent: 4471373 (1984-09-01), Shimizu et al.
patent: 4780424 (1988-10-01), Holler et al.
patent: 5104819 (1992-04-01), Freiberger et al.
patent: 5449629 (1995-09-01), Kajita
patent: 5550072 (1996-08-01), Cacharelis et al.
patent: 5756385 (1998-05-01), Yuan et al.
IEEE IEDM Technical Digest 93, 1993 pp. 321-324, Hsing-Huang Tsend et al., "Thin CVD Stacked Gate Dielectric For ULSI Technology".

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