Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-05-10
2011-05-10
Nguyen, Khiem D (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S311000, C257S347000, C257SE21426, C257SE21618
Reexamination Certificate
active
07939412
ABSTRACT:
An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher VTlying between a portion associated with a relatively lower VTand the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher VTof the channel region. A process for forming the electronic device is also disclosed.
REFERENCES:
patent: 4701423 (1987-10-01), Szluk
patent: 5384473 (1995-01-01), Yoshikawa et al.
patent: 6166413 (2000-12-01), Ono
patent: 6765303 (2004-07-01), Krivokapic et al.
patent: 6815277 (2004-11-01), Fried et al.
patent: 6867460 (2005-03-01), Anderson et al.
patent: 6909147 (2005-06-01), Aller et al.
patent: 6987289 (2006-01-01), Nowak
patent: 6992354 (2006-01-01), Nowak et al.
patent: 7045401 (2006-05-01), Lee et al.
patent: 7074662 (2006-07-01), Lee et al.
patent: 7112455 (2006-09-01), Mathew et al.
patent: 7214576 (2007-05-01), Kaneko et al.
patent: 7224029 (2007-05-01), Anderson et al.
patent: 7244029 (2007-07-01), Anderson
patent: 7382020 (2008-06-01), Liu et al.
patent: 7575975 (2009-08-01), Thean et al.
patent: 7709303 (2010-05-01), Burnett et al.
patent: 2004/0113207 (2004-06-01), Hsu et al.
patent: 2004/0222477 (2004-11-01), Aller et al.
patent: 2005/0184316 (2005-08-01), Kim et al.
patent: 2005/0239242 (2005-10-01), Zhu et al.
patent: 2006/0068531 (2006-03-01), Breitwisch et al.
patent: 2006/0113522 (2006-06-01), Lee et al.
patent: 2006/0151834 (2006-07-01), Anderson et al.
patent: 2006/0177977 (2006-08-01), Chan et al.
patent: 2007/0093010 (2007-04-01), Mathew et al.
patent: 2007/0158764 (2007-07-01), Burnett et al.
patent: 2007/0269950 (2007-11-01), Anderson et al.
U.S. Appl. No. 12/785,829, filed May 24, 2010, entitled “Integrated Circuit Using Finfets and Having a Static Random Access Memory (SRAM)”.
Doris et al., “A Simplified Hybrid Orientation Technology (SHOT) for High Performance CMOS,” 2004 IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 86-87.
Yang et al., “On the Integration of CMOS with Hybrid Crystal Orientations,” 2004 IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 160-161.
Non-Final Office Action mailed Dec. 29, 2010 for U.S. Appl. No. 12/785,829, 15 pages.
Burnett James D.
Orlowski Marius K.
Freescale Semiconductor Inc.
Nguyen Khiem D
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