Process for forming a transistor with a nonuniformly doped chann

Details Process for forming a transistor with a nonuniformly doped chann Process for forming a transistor with a nonuniformly doped chann

1996-05-13

1998-04-21

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438304, 438305, 438531, 438596, 438944, H01L 21336

Patent

active

057417369

ABSTRACT:
A semiconductor device (83)including a transistor (85) with a nonuniformly doped channel region can be formed with a relatively simple process without having to use high dose implants or additional heat cycles. In one embodiment, a polysilicon layer (14) and silicon nitride layer (16) are patterned at the minimum resolution limit. The polysilicon layer is then isotropically etched to form a winged gate structure (32). A selective channel implant step is performed where ions are implanted through at least one of the nitride wings of the winged gate structure (32) but are not implanted through the polysilicon layer (14). Another polysilicon layer (64)is conformally deposited and etched such that the polysilicon (74) does not extend beyond the edges of the nitride wings.

REFERENCES:
patent: H986 (1991-11-01), Codella et al.
patent: 4198250 (1980-04-01), Jecmen
patent: 4404576 (1983-09-01), Ronen
patent: 4442589 (1984-04-01), Doo et al.
patent: 4558338 (1985-12-01), Sakata
patent: 4679311 (1987-07-01), Lakhani et al.
patent: 4682404 (1987-07-01), Miller et al.
patent: 4727038 (1988-02-01), Watabe et al.
patent: 4801555 (1989-01-01), Holly et al.
patent: 4933994 (1990-06-01), Orban
patent: 5024959 (1991-06-01), Pfeister
patent: 5053849 (1991-10-01), Izawa et al.
patent: 5151374 (1992-09-01), Wu
patent: 5155563 (1992-10-01), Davies et al.
patent: 5202276 (1993-04-01), Mamli
patent: 5213989 (1993-05-01), Fitch et al.
patent: 5227321 (1993-07-01), Lee et al.
patent: 5272100 (1993-12-01), Satoh et al.
patent: 5316961 (1994-05-01), Okazawa
patent: 5364807 (1994-11-01), Hwang
patent: 5371394 (1994-12-01), Ma et al.
patent: 5372960 (1994-12-01), Davies et al.
patent: 5427964 (1995-06-01), Kaneshiro et al.
patent: 5441906 (1995-08-01), Burger
patent: 5451807 (1995-09-01), Fujita
patent: 5482878 (1996-01-01), Burger et al.
patent: 5484743 (1996-01-01), Ko et al.
patent: 5510279 (1996-04-01), Chien et al.
patent: 5604138 (1997-02-01), Lee et al.
patent: 5604139 (1997-02-01), Codama et al.
T.N. Buti, et al., IEEE Trans. Electron Dev., 38, 8 (1991) 1757, "A New Asymmetrical halo Source Gold Drain . . .MOSFET . . ." Aug. 1991.
S.N. Chakravarti, et al., IBM Tech. Discl. Bulletin, 19, 4 (1976) 1162, "DMOSFET" Sep. 1976.
Translations of JP 53-112069, 62-29166, 4-180633 Sep 1978.
S. Wolf, "Silicon Processing For the VLSI Era" vol II, 1992, pp. 144-147, 356-363.
Wolf; "Silicon Processing For the VLSI Era, vol. 2-Process Integration;" Lattice Press; pp. 348-55; (1990).
Luscher, et al; "SACMOS, A New Procedure for High Density Integrated Circuits"; Revue Polytechnique No. 5; pp. 455-57 (1985).
Luscher et al; "A High Density CMOS Process"; ISSCC pp. 260-261 & 361 (1985).

Affiliated with

Also associated with

Rating

Process for forming a transistor with a nonuniformly doped chann does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for forming a transistor with a nonuniformly doped chann, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for forming a transistor with a nonuniformly doped chann will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2057295