Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-04-29
2004-06-01
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S287000, C438S591000, C438S769000, C438S785000
Reexamination Certificate
active
06743668
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of fabricating a semiconductor structure, and more particularly to a process for forming a metal oxy-nitride dielectric layer.
DESCRIPTION OF RELATED ART
In an effort to make faster transistors, the dimensions of Metal Oxide Semiconductor Field Effect Transistors (MOSFET) have continually scaled down. A thin and critical layer of the MOS transistor is the gate dielectric. Current gate dielectric thicknesses are near 3 nanometers (nm) and are rapidly scaling down to the sub-2 nm regime.
The study of high permittivity gate dielectrics for its application in Complimentary Metal Oxide Semiconductor (CMOS) technologies has recently intensified. The increased interest in high permittivity gate dielectrics is due to the semiconductor industry's realization that conventional silicon dioxide (SiO
2
) gate dielectrics will not meet the gate leakage requirements when the dielectric thickness is in the sub-2 nm regime. Within this regime, the gate dielectric is about 13 atoms thick and results in gate leakage currents that exceed industry specifications for low power consumption products.
A solution to the problem of gate leakage currents as the dimensions of MOSFET continue to scale down, is to manufacture MOS transistors using gate dielectrics with permittivities higher than SiO
2
, such as metal oxide materials. With high permittivity gate dielectrics, the overall dielectric thickness is increased, thus reducing a direct tunneling effect without sacrificing gate capacitance. Unfortunately, there are many issues associated with the integration of metal oxide dielectrics into CMOS technologies. For example, metal oxide dielectrics have worse gate leakage properties than SiO
2
films of equivalent physical thickness. In addition, metal oxide dielectrics exhibit poor thermal stability. In standard CMOS integration techniques, the gate dielectric is subjected to subsequent high temperature annealing (>1000 C.) for the source and drain dopant activation. During the source and drain anneals, the metal oxide dielectric reacts with the silicon substrate forming an undesirable SiO
2
interfacial region between the silicon and the metal oxide dielectric.
Other thermal stability issues involve film microstructure. Annealing at such extreme temperatures can cause amorphous metal oxide dielectric films to crystallize. This phase transition roughens the dielectric surface, causing increased trapping density and leakage via grain boundaries. The phase transition also increases the propensity for boron diffusion from the gate electrode to the substrate. Boron penetration through the gate dielectric into the substrate results in high threshold voltage shifts and reliability problems.
Further, the metal oxide dielectrics frequently exhibit capacitive hysteresis as indicated by a capacitance versus voltage graph of the metal oxide dielectric layer. The hysteresis is an undesirable trait indicating instability in the threshold voltage and lack of control over the channel region by the gate voltage.
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Nguyen Bich-Yen
Raymond Mark V.
Schaeffer, III James K.
Duy Mai Anh
Fahmy Wael
Motorola Inc.
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