Process for forming a high density semiconductor device

Details Process for forming a high density semiconductor device Process for forming a high density semiconductor device

1999-01-22

2001-03-20

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06204112

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit device and a method for the fabrication thereof, and, more particularly, to a memory device having a compact cell design with a deep trench storage capacitor self-aligned to the gate conductor cap insulator of the access transistor and connected by a buried strap.
2. Discussion of the Related Art
Semiconductor memory devices, and particularly Dynamic Random Access Memory (DRAM) devices are well known. An essential feature of a DRAM is a memory cell. A cell comprises a capacitor for storing charge and an access transistor (also referred to as a pass transistor or a pass gate) for transferring charge to and from the capacitor. Trench, or deep trench (DT), capacitors are typical and are well known. A cell also comprises a means (often referred to as a strap) for connecting one transistor source/drain region to the capacitor. At the present state of the art, more than 64 million DRAM cells are present on a memory chip, organized in the form of an array. Thus, because cell size determines chip density, size and cost, reducing cell area is the DRAM designer's primary goal. Cell area may be reduced by shrinking the individual feature size, or by forming structures which make more efficient use of the chip surface area. The latter approach is particularly desirable.
In a typical process for fabricating DRAM devices having trench capacitors, the capacitor structure is completely formed prior to the formation of the transistor gate conductor (GC) structure. Thus, a typical process sequence involves the steps of opening the trench, filling the trench, forming the node conductors, then forming the gate stack structure. It will be understood that a separate lithographic step is required for gate stack definition, which may lead to overlay and other errors. Thus, using known fabrication processes, a larger surface area must be included in the cell structure to provide tolerance for such errors.
It is accepted practice in the DRAM cell art to connect a trench capacitor to a transistor by means of a surface strap. However, low process tolerances for the steps of forming the surface strap may lead to an increased incidence of shorts between a surface strap and an adjacent gate conductor. Therefore, it is often preferred to provide a buried strap for connecting the source/drain region of the transistor to the capacitor. Where the strap is buried, more room is available on the surface of the semiconductor device and higher device densities may be obtained. Moreover, since the buried strap contacts are formed prior to formation of many other structures, potential damage to other surface structures is minimized. Nevertheless, known processes for forming buried straps still provide for forming the gate conductor in a separate lithographic step after trench capacitor formation, and thus are not self-aligned.
The following references are representative of the prior art.
U.S. Pat. No. 5,336,629 to Dhong, et al., describes a folded bitline DRAM cell in which the access transistor is placed vertically over the trench capacitor by growing a silicon epitaxial layer over the trench region. Thereafter an ohmic contact between the source diffusion of the access transistor and the trench capacitor is made laterally via sidewall P+ polysilicon straps stemming from the trench polysilicon electrode.
U.S. Pat. No. 4,988,637 to Dhong, et al., describes a DRAM cell, which includes a trench storage capacitor buried in the substrate juxtaposed to the access transistor, that is formed by an epitaxial silicon growth and a mesa etch process. The contact between the two elements is established via a doped polysilicon strap formed over the buried trench in the mesa region which is butted against the access transistor source situated in the epitaxial silicon region.
U.S. Pat. No. 5,389,559 to Hsieh, et al., describes a DRAM cell process having the conventional structure of an access transistor whose source diffusion is ohmically connected to the trench storage capacitor via a buried strap comprising of an outdiffused doped region from doped polysilicon layer on the trench sidewall.
U.S. Pat. No. 4,894,696 to Takeda, et al., describes a DRAM cell process in which the memory cell capacitor is comprised of a trench which is situated at a position defined by a device isolation region on one side and the access transistor gate on the other side. However, the depth of the trench is limited to 2 microns and subsequently, a P+ guardband (HiC) layer is developed around the trench to decrease the alpha particle induced soft error problem in the cell. The contact from the storage node electrode to the access transistor source diffusion is made through an N+ poly doped polysilicon layer In the trench. The dielectric layers for the capacitance are then deposited consisting of films, e.g. single or multilayer SiO
2
/Si
3
N
4
/SiO
2
or Ta
2
O
5
. Thereafter, the plate of the capacitor consisting of a P+ or N+ polysilicon layer is defined consisting of polysilicon deposition and lithography steps. The trench process requires a number of high temperature process steps which are deleterious to previously formed implant regions and may cause outdiffusion of implanted species.
U.S. Pat. No. 5,429,978 to Lu, et al., is similar to U.S. Pat. No. 4,894,696 to Takeda, et al., in that the storage trench capacitance of the DRAM cell is self-aligned to the device isolation region on one side and the access transistor gate on the other side. The trench capacitor is made of a pillar type trench structure for increased capacity. The contact to the access transistor source node is made through a wraparound N+ layer formed by outdiffusion of a doped PSG layer deposited in the trench.
Even in view of the known art, there still exists a continuing demand for semiconductor memory device designs and processes which utilize fewer processing sequences, while at the same time facilitating greater storage capacity and allowing more densely packed memory arrays. There further exists a need for a trench capacitor structure which is self-aligned to the gate conductor and is connected by means of a buried strap. Thus, it would be desirable to provide a method for satisfying such demand and solving the aforesaid and other deficiencies and disadvantages.
SUMMARY OF THE INVENTION
An object of the present invention is to overcome the problems in the art discussed above.
Another object of the present invention is to provide a semiconductor device and method for the manufacture thereof having increased chip density.
Another object of the present invention is to provide a semiconductor memory cell structure and method for the manufacture thereof having decreased cell size.
Another object of the present invention is to provide a semiconductor memory cell structure and method for the manufacture thereof having a buried strap rather than a surface strap.
Another object of the present invention is to provide a semiconductor memory cell structure and method for the manufacture thereof having a deep trench capacitor placed adjacent to the gate by a self-aligned process.
Still, yet another object of the present invention is to provide a semiconductor memory cell structure and method for the manufacture thereof having a trench storage node capacitor which is fabricated subsequent to the formation of the gate stack.
Thus, according to the present invention, the method for forming a semiconductor device comprises the steps of:
a) obtaining a semiconductor device substrate having at least one patterned gate conductor and at least one patterned cap insulator thereon;
b) forming a dielectric masking layer over the at least one cap insulator;
c) forming at least one opening in the dielectric masking layer;
d) using the at least one opening in the dielectric masking layer as a mask, forming at least one opening in the substrate for a capacitor.
The method may optionally comprise the additional steps of:
e) forming a layer

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