Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-20
2001-05-22
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000
Reexamination Certificate
active
06235580
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to methods used to fabricate semiconductor devices, and more specifically to a process used to form a crown shaped, capacitor structure, for a dynamic random access memory, (DRAM), device.
(2) Description of Prior Art
To increase performance of DRAM devices, the semiconductor industry has concentrated on increasing the signal, or capacitance, of the DRAM capacitor structure. The use of crown shaped, or cylindrical shaped, stacked capacitor structures, has allowed the desired capacitance increases to be realized via the additional surface area offered with the use of crown shaped storage node structures. However the topography of the crown shaped storage node structure, can lead to difficulties when attempting to fabricate a polysilicon capacitor upper plate structure, overlying the severe underlying topography. The definition of the polysilicon capacitor upper plate structure, via conventional photolithographic and dry etching procedures, is aggravated by the height of the vertical features, and by the spaces between the vertical features, of the underlying crown shaped storage node structure. The use of thick photoresist layers, needed to insure filling of the spaces between the vertical features of the crown shaped storage node structures, can result in a decreasing resolution of photoresist shape used to define the capacitor upper plate structure. In addition the anisotropic, reactive ion etching, (RIE), needed to define the capacitor upper plate structure, becomes more difficult when attempting to remove regions of polysilicon located on the vertical sides of the underlying crown shaped storage node structures.
This invention will describe a process for creating a crown shaped capacitor structure, featuring the use of a spin-on glass, (SOG), layer, used overlying the polysilicon layer that will be subjected to the definition procedures used for the polysilicon capacitor upper plate structure. The use of the planarizing SOG layer alleviates the severity of the subsequent photolithographic and dry etching procedures, used for definition of the capacitor upper plate structure. After definition of the polysilicon, capacitor upper plate structure, for the crown shaped capacitor structure, the SOG layer is selectively removed via use of a buffered hydrofluoric acid solution. Prior art such as Matsuura, in U.S. Pat. No. 5,937,322, as well as Lin et al, in U.S. Pat. No. 5,700,731, describe processes for fabricating crown shaped capacitor structures, however those prior arts do not describe the novel use of a disposable SOG layer, normalizing the severe topography of the underlying crown shaped storage node structure, reducing the severity of subsequent photolithographic and RIE procedures, used to define an overlying polysilicon capacitor upper plate structure.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a crown shaped capacitor structure for a DRAM device.
It is another object of this invention to use a SOG layer to fill the spaces between the vertical features of the crown shaped storage node structures, after deposition of the polysilicon layer, allowing photolithographic and dry etrching procedures, used to definer the polysilicon capacitor upper plate structure, to be performed on a less severe topography.
It is still another object of this invention to define the capacitor upper plate structure, in the SOG layer, and in the underlying polysilicon layer, via a photolithographic and RIE procedure, followed by selective removal of the SOG layer from the underlying polysilicon, capacitor upper plate structure.
In accordance with the present invention a process for fabricating a crown shaped capacitor structure, for a DRAM device, featuring a disposable SOG layer, used to reduce the topography created by underlying crown shaped storage node structures, prior to the subsequent definition of a capacitor upper plate structure, is described. Polysilicon, crown shaped storage node structures are formed, overlying, and contacting, conductive plug structures, which in turn overlay, and contact, active device regions in the transfer gate transistors. After formation of a capacitor dielectric layer, and an overlying polysilicon layer, on the crown shaped storage node structures, a SOG layer is applied on the underlying polysilicon layer, filling the spaces between the vertical features of the crown shaped storage node structures. After a partial etch back of the SOG layer, a photoresist shape, used for subsequent definition of a polysilicon, capacitor upper plate structure, is formed on the thinned SOG layer. A wet etch procedure is used to remove SOG layer, exposed in an opening in the photoresist shape, exposing a portion of the polysilicon layer, located between the vertical features of the crown shape storage node structures. An anisotropic RIE procedure is next employed to remove the exposed regions of the polysilicon layer, resulting in the definition of the polysilicon, capacitor upper plate structure. After removal of the photoresist layer, used for definition of the capacitor upper plate structure, another wet etch dip is used to remove remaining areas of the SOG layer.
REFERENCES:
patent: 5700731 (1997-12-01), Lin et al.
patent: 5753547 (1998-05-01), Ying
patent: 5821141 (1998-10-01), Huang
patent: 5893734 (1999-04-01), Jeng et al.
patent: 5937322 (1999-08-01), Matsuura
patent: 6083831 (2000-07-01), Dennison
Chiang Wen-Chuan
Lee Yu-Hua
Wu Cheng-Ming
Ackerman Stephen B.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Tsai Jey
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