Process for forming a borderless via in a semiconductor device

Details Process for forming a borderless via in a semiconductor device Process for forming a borderless via in a semiconductor device

2000-01-13

2001-11-20

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S625000, C438S629000, C438S631000, C438S633000, C438S634000, C438S672000, C438S675000, C438S666000, C438S671000

Reexamination Certificate

active

06319823

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial No. 88117962, filed Oct. 18, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating an integrated circuit. More particularly, the present invention relates to a method for forming a borderless via in a semiconductor device.
2. Description of the Related Art
Before the development of techniques for forming deep sub-micron semiconductor devices, critical dimension (CD) of devices used to be quite large. Although there is some misalignment in a photolithographic process so that the vias are slightly offset, later-formed contacts can still land on the desired metal conductive lines. Operating characteristics of the device are affected very little by the misalignment.
FIG. 1
is a schematic, cross-sectional view showing an interconnect structure according to the prior art. As shown in
FIG. 1
, a plug
118
is formed on a metal conductive line
104
. The plug
118
is a conductive structure in a via
114
formed in an inter-metal dielectric (IMD) layer
112
. A structure between the metal conductive line
104
and a substrate
100
is another IMD layer or an interlayer dielectric layer
102
.
Therefore, when techniques for fabricating deep sub-micron devices are employed, critical dimensions of devices shrink considerably. A very small misalignment of the via
114
or the plug
118
to the conductive line
104
often can have considerable effect on the operating characteristics of the devices. Thus, alignments of the via
114
and the plug
118
to the conductive line
104
become critical, especially when the desired dimension of the device exceeds or approaches the acceptable tolerance of the fabricating equipment. Hence, the conventional method is incapable of fabricating a via or a plug that lands exactly on the desired location according to deep-submicron device specification.
Therefore, innovative techniques for forming a borderless via or plug are required in order to fabricate a deep submicron device. In particular, the formation of interconnects between a large number of layers to form a multi-level interconnect (MLM) system depends very much on the capacity to form the high-quality borderless via or plug.
In addition, according to the prior art, an over-etching process is required in the fabrication of an interconnect structure. However, in the over-etching process, a metal conductive line is exposed, and the exposed metal conductive line reacts with an etching agent. The contact resistance Rc of the via is thus increased.
SUMMARY OF THE INVENTION
According to above, the invention provides an improved process for forming a borderless via in a semiconductor device. The process comprises the following steps. A conductive layer, a borophosphosilicate glass (BPSG) layer and a patterned first photoresist mask layer are formed in a dielectric layer in sequence. The BPSG layer is patterned into a BPSG plug while using the patterned first photoresist mask layer as a mask. A second photoresist mask layer is formed to cover the patterned first photoresist mask layer and the metal layer. The conductive layer is defined to form a conductive line beneath the BPSG plug and the second mask layer. The first and second photoresist mask layers are removed. An inter-metal dielectric layer is formed around the BPSG plug and the conductive line. A via is formed in the inter-metal dielectric layer by removing the BPSG plug. A barrier layer and a metal layer fill the via to form a metal plug.
Thus, in the invention, the via process of the multi-layer interconnection can be successfully performed even if a misalignment occurs.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5518963 (1996-05-01), Park
patent: 5721155 (1998-02-01), Lee

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