Process for formation of trench in integrated circuit structure

Details Process for formation of trench in integrated circuit structure Process for formation of trench in integrated circuit structure

1984-11-05

1987-01-27

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29576W, 29580, 148187, 156646, 156648, 156651, 156653, 156657, 1566591, 156662, 20419232, 427 93, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

046392882

ABSTRACT:
An improved process is disclosed for making an integrated circuit structure wherein a trench is etched into one or more layers to electrically separate one of the devices in the integrated circuit structure from other portions thereof by first patterning silicon dioxide and silicon nitride layer on a layer of silicon. The improvement comprises isotropically etching the silicon layer to provide an enlarged shallow etch area undercutting the patterned silicon dioxide and silicon nitride layers. Subsequent deeper anisotropic etching to form the trench will result in a trench having an enlarged upper width which, in turn, prevents the formation of voids adjacent the upper portion of the trench during subsequent oxidation and polysilicon deposition steps. Possible creation of openings to such voids in the polysilicon during subsequent planarization is thereby eliminated thus avoiding undesirable oxidation of such voids and undesirable stress formation therefrom.

REFERENCES:
patent: 4472240 (1984-09-01), Kameyama

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