Process for formation of isolation trenches with high-K gate die

Details Process for formation of isolation trenches with high-K gate die Process for formation of isolation trenches with high-K gate die

1998-08-07

1999-12-28

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438240, 438287, H01L 218242, H01L 2170

Patent

active

060080957

ABSTRACT:
A process for formation of isolation trenches with high-k gate dielectrics. In an example embodiment, the process comprises depositing a high permittivity layer on the substrate. An isolation trench extending from the high permittivity layer into the substrate is etched at a selected location on the substrate. The high permittivity layer is then etched to a selected thickness, and gate electrodes are formed adjacent the trench on the high permittivity layer of the selected thickness. In another embodiment, the isolation trench is formed with an oxide liner using an NO anneal, and the high-K gate dielectric layer is optionally reduced in thickness.

REFERENCES:
patent: 5292673 (1994-03-01), Shinriki et al.
patent: 5420060 (1995-05-01), Gill et al.
patent: 5679599 (1997-10-01), Mehta
patent: 5741722 (1998-04-01), Lee
patent: 5763310 (1998-06-01), Gardner
patent: 5777370 (1998-07-01), Omid-Zohoor et al.
patent: 5786256 (1998-07-01), Gardner et al.
patent: 5834348 (1998-10-01), Kwon et al.

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