Process for flash memory cell

Details Process for flash memory cell Process for flash memory cell

2005-02-01

2005-02-01

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S260000, C438S201000, C257S315000, C257S321000

Reexamination Certificate

active

06849499

ABSTRACT:
A method is provided for forming a flash memory cell having an amorphous silicon floating gate capped by a CVD oxide, and a control gate formed over an intergate oxide layer formed over the oxide cap. Amorphous silicon is first formed over a gate oxide layer over a substrate, followed by the forming of a silicon nitride layer over the amorphous silicon layer. Silicon nitride is patterned to have a tapered opening so that the process window for aligning the floating gate with the active region of the cell is achieved with a relatively wide margin. Next, an oxide cap is formed over the floating gate. Using an oxide deposition method in place of the conventional polyoxidation method provides a less bulbous oxide formation over the floating gate, thus, yielding improved erase speed for the cell. The invention is also directed to a flash memory cell fabricated by the disclosed method.

REFERENCES:
patent: 4861730 (1989-08-01), Hsia et al.
patent: 5453388 (1995-09-01), Chen et al.
patent: 5597751 (1997-01-01), Wang
patent: 5736443 (1998-04-01), Park et al.
patent: 5783473 (1998-07-01), Sung
patent: 6090668 (2000-07-01), Lin et al.

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