Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2005-01-25
2005-01-25
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C257S734000, C257S735000, C257S736000
Reexamination Certificate
active
06846719
ABSTRACT:
A wafer bump fabrication process is provided in the present invention. A wafer with multiple bonding pads and a passivation layer, which exposes the bonding pads, is provided. The surface of each bonding pad has an under bump metallurgy layer. A patterned photoresist layer with a plurality of opening is formed which openings expose the under bump metallurgy layer. Afterwards a curing process is performed to cure the patterned photoresist layer. Following a solder paste fill-in process is performed to fill a solder paste into the openings. A reflow process is performed to form bumps from the solder paste in the openings. The patterned photoresist layer is removed.
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Chen Jau-Shoung
Chou Yu-Chen
Fang Jen-Kuang
Huang Min-Lung
Lee Chun-Chi
Advanced Semiconductor Engineering Inc.
Ha Nathan W.
Jiang Chyun IP Office
Pham Long
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