Process for fabricating vertical transistors

Details Process for fabricating vertical transistors Process for fabricating vertical transistors

1999-06-18

2001-03-06

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S138000

Reexamination Certificate

active

06197641

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention is directed to a process for fabricating vertical transistors.
2. Art Background
In integrated circuits, there is a trend toward a higher device density to increase the number of devices per unit area. Device density is increased by making individual devices smaller and placing the devices closer together. Device dimensions (termed feature size or design rules) are decreasing from 0.25 &mgr;m to 0.18 &mgr;m and beyond. It is also desired to decrease the distance between devices in a commensurate fashion.
Currently, most MOS (metal oxide semiconductor) transistors have a planar configuration. In a planar MOS device, the direction of the current flow is parallel to the plane of the substrate surface. Although there is a need to decrease the size of these devices to achieve increased device density, fabricating these small devices becomes increasingly difficult. In particular, lithography becomes extremely difficult as device dimensions decrease to less than the wavelength of the radiation used to delineate an image of a pattern in a radiation-sensitive material.
A vertical device configuration, described in Takato, H., et al., “Impact of Surrounding Gate Transistor (SGT) for Ultra-High-Density LSI's”
IEEE Transactions on Electron Devices
, Vol. 38 (3), pp. 573-577 (1991) has been proposed as an alternative to the more space-consuming planar device configuration. A schematic of the device is illustrated in FIG.
1
. The device
10
has a source
15
, drain
20
, and channel
25
. The length of the channel
25
is perpendicular to the surface of the substrate
30
on which the device
10
is formed. The device is called a vertical transistor because the length of the channel is perpendicular to the substrate surface. A gate
35
surrounds the channel
25
.
Although vertical MOSFETs (metal oxide semiconductor field effect transistors) can be packed more densely than planar MOSFETs, the processing issues for the vertical transistors are not trivial. A process that makes it easier and more efficient to fabricate vertical MOSFETs is therefore desired.
SUMMARY OF THE INVENTION
The present invention is directed to a process for fabricating a vertical MOSFET. In the process, a multilayer stack of material is formed on a semiconductor substrate. Examples of suitable semiconductor substrates include silicon substrates and silicon on insulator (SOI) substrates. The surface region of the silicon substrate has been heavily doped (i.e., a dopant concentration in excess of 1×10
19
atoms/cm
3
of dopant). The multilayer stack of material has at least three layers. The first layer is an electrically insulating material, e.g. silicon nitride. The first layer of insulating material has a thickness in the range of about 25 nm to about 250 nm. The thickness of the first layer is selected so that the capacitance between the gate and the source or drain (depending upon which of the source or the drain is formed in the substrate) is sufficiently low. This consideration favors a thickness within the higher portion of the above-described range. The thickness of the first layer is also selected so that the series resistance of the source/drain extension is sufficiently low and that outdiffusion from the heavily doped region of the substrate to form the source/drain extension is readily accomplished. These considerations favor a thickness within the lower portion of the above-described range. One skilled in the art will be able to select a suitable thickness based upon the above-described considerations, as well as other considerations that apply to specific embodiments.
A second layer of material is formed over the first layer of material. However, the material of the second layer (e.g., silicon dioxide (SiO
2
)) has a significantly different etch resistance to a selected etchant than the insulating material of the first layer. Specifically, for the selected etchant, the etch rate of the material of the second layer is much higher than the etch rate of the insulating material of the first layer. It is advantageous if the etch rate of the second layer of material in the selected etchant is at least about ten times faster than the etch rate of the first layer of material. For the selected etchant, the etch rate of the material of the second layer is also at least ten times faster than the etch rate of a semiconductor material in which the channel of the device is formed. Crystalline silicon is one example of such a semiconductor material. It is advantageous if the etch rate of the material of the second layer is at least 100 times faster than the etch rate of the semiconductor material.
The thickness of the second layer of material is selected to define the physical gate length of the device. This is because this second layer is sacrificial, i.e., it will be removed and the gate of the device will be formed in the space defined by this layer. Defining the gate length in this manner provides much better gate length control than is achievable using conventional lithographic techniques and subsequent pattern transfer using dry etch techniques.
A third layer of material is formed over the second layer. The material selected for the third layer is an electrically insulating material. It is advantageous if the insulating material in the third layer has a lower etch rate in the selected etchant than the material of the second layer. It is advantageous if the ratio of the etch rate, in the selected etchant, of the material in the second layer to the etch rate of the material in the third material layer is at least ten to one. From the standpoint of ease of processing, it is advantageous if the material of the first layer is the same as the material of the third layer.
The top layer in the at least three-layer stack is a stop layer that protects the underlying structure from subsequent processing (e.g. chemical mechanical polishing). If the third layer is not a suitable stop for subsequent chemical mechanical polishing, a fourth layer (e.g. silicon nitride) is then formed over the structure. The fourth layer also acts as a dopant diffusion barrier. Specifically, the layer prevents dopant diffusion from material underlying the fourth layer into material overlying the fourth layer or into the ambient during subsequent processing.
A window or trench (referred to simply as a window hereinafter) is then etched through the three-layer structure (for simplicity, this description will simply refer to the three layer structure) to the heavily-doped surface of the silicon substrate. The dimensions of the window are determined by the size constraints for the particular device and the limitations of the lithographic techniques used to form the window. The window is formed using conventional lithographic techniques. Specifically, a mask is formed over the three-layer structure by forming a layer of an energy-definable material thereon and introducing an image of a pattern into the layer of energy-definable material therein. The pattern is then developed and the only portion of the three-layer structure exposed through the mask is the portion that corresponds to the dimensions and placement of the desired window or trench. The window is then etched into the three-layer structure. After the window is etched, the portions of the mask remaining on the substrate surface are removed using conventional expedients well known to one skilled in the art.
The window is then filled with a semiconductor material. Although the semiconductor material is either crystalline, polycrystalline, or amorphous, typically the semiconductor material is a crystalline material such as silicon, silicon-germanium, or silicon-germanium-carbon. The crystalline semiconductor material need not be uniform in composition. The crystalline semiconductor material is either doped or undoped. Techniques for forming crystalline semiconductor materials in windows are well known to one skilled in the art. For example, in one technique, the crystalline material is formed in the window or tren

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