Process for fabricating vertical transistors

Details Process for fabricating vertical transistors Process for fabricating vertical transistors

1998-08-28

2000-02-22

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438138, H01L 21336

Patent

active

060279753

ABSTRACT:
A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer.
After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers. The window terminates at the surface of the silicon substrate in which one of either a source or drain region is formed in the silicon substrate. The window or trench is then filled with a semiconductor material. This semiconductor plug becomes the vertical channel of the transistor. Therefore the crystalline semiconductor plug is doped to form a source extension, a drain extension, and a channel region in the plug. Subsequent processing forms the other of a source or drain on top of the vertical channel and removes the sacrificial second material layer. The removal of the sacrificial second layer exposes a portion of the doped semiconductor plug. The device gate dielectric is then formed on the exposed portion of the doped semiconductor plug. The gate electrode is then deposited. The physical gate length of the resulting device corresponds to the deposited thickness of the second material layer.

REFERENCES:
patent: 4670768 (1987-06-01), Sunami et al.
patent: 5733811 (1998-03-01), Yamazaki
patent: 5872037 (1999-02-01), Iwamatsu et al.
patent: 5918155 (1999-06-01), Kikuchi et al.
patent: 5943574 (1999-08-01), Tehrani et al.
IEEE Transactions on Electron Devices, vol. 38, No. 3, "Impact of Surrounding Gate Transistor (SGT) for Ultra-High-Density LSI's", H. Takato et al., pp. 573-577, Mar. 1991.
IEEE Transactions on Electron Devices, vol. 42, No. 12, "Impact of a Vertical .PHI.-Shape Transistor (V.PHI.T) Cell for 1 Gbit DRAM and Beyond", S. Maeda et al., pp. 2117-2123, Dec. 1995.
Solid State Technology, "Nano-MOSFETs for Future ULSI Application", A. Strass, pp. 65-74, Jan. 1996.
IEDM, "Sub-50 NM Gate Length N-Mosfets With 10 NM Phosphorus Source And Drain Junctions", M. Ono et al., pp. 6.2.1-6.2.4, 1993.
IEDM, "An SPDD P-Mosfet Structure Suitable For 0.1 and Sub 0.1 Micron Channel Length and its Electrical Characteristics", M. Saito, et al., pp. 35.5.1-35.5.4, 1992.
54.sup.th Device Research Conference, "Vertical, Fully-Depleted, Surrounding Gate Mosfets on sub-0.1 .mu.m Thick Silicon Pillars", C. Auth et al., pp. 108-109, Jun. 24-26, 1996.

Affiliated with

Also associated with

Rating

Process for fabricating vertical transistors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for fabricating vertical transistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating vertical transistors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-520041