Process for fabricating SOI compact contactless flash memory cel

Details Process for fabricating SOI compact contactless flash memory cel Process for fabricating SOI compact contactless flash memory cel

1997-01-24

1999-03-23

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438263, 438149, H01L 21336

Patent

active

058858687

ABSTRACT:
A process for fabricating compact contactless flash memory array for semiconductor EEPROM devices having a number of memory cell units is disclosed. Field oxide layers for the flash memory array are first grown over the surface of an SOI wafer. Gate oxide layers are then grown. Floating gates are then formed by patterning the first polysilicon layer. Source/drain buried bitlines for the flash memory array are formed. A first BPSG (borophosphosilicate glass) layer is deposited and then reflown and etched back. An oxide-nitride-oxide layer is formed. A second polysilicon layer is deposited with in-situ dope. A WSi.sub.x layer then forms. Stacked gates for the flash array are formed by patterning into the formed oxide-nitride-oxide, second polysilicon and WSi.sub.x layers. The stacked gates are then covered with a second BPSG layer. Contact openings for the source/drain buried lines are formed. Metal lines leading into the contact openings are then formed for interconnecting the memory cells in the flash memory array with peripheral control circuits of the semiconductor EEPROM devices.

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"A Novel Memory Cell Using Flash Array Contactless EPROM (FACE) Technology," 1990 IEDM, pp. 90-94.
"A NAND Structured Cell With A New Programming Technology For Highly Reliable 5-V Only Flash EEPROM," 1990 Symposium on VLSI Technology, pp. 129-130.

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