Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-02-06
2001-08-14
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S290000
Reexamination Certificate
active
06274439
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a fabrication technology for a semiconductor device and, more particularly, to a process for fabricating a semiconductor device with field effect transistors changeable in threshold voltage with hydrogen ion after formation of wiring strips on an inter-level insulating structure.
DESCRIPTION OF THE RELATED ART
It is very important to precisely control the threshold voltage of a field effect transistor. When the threshold voltage is as close to a design value as possible, the field effect transistor exhibits the design transistor characteristics such as the switching speed and the amount of leakage current. Various factors affect the threshold voltage, and are, by way of example, the thickness of the gate insulating layer, the width of the gate electrode and the amount of dopant impurity introduced in the channel region. These factors tend to fluctuate during the fabrication process. With the decrease in the size of field effect transistor is getting smaller and smaller, the control of fluctuation becomes very difficult. The manufacturer can evaluate the field effect transistors only after a metal wiring structure is formed over the field effect transistors. If it is possible to correct the threshold voltage after the metallization according to the measured value, the manufacturer rescues defective field effect transistors from rejection, and the production yield is improved.
Field effect transistors different in threshold voltage are usually incorporated in a semiconductor integrated circuit device. When leakage current is needed to be low, the threshold voltage of field effect transistor is set at a high value. On the other hand, a high-speed field effect transistor is designed to have low threshold voltage. A mask ROM (read only memory) device has memory cells selectively programmed in logic “1” level and logic “0” level, and the memory cell is implemented by a field effect transistor. The two logic levels are corresponding to a high threshold voltage and a low threshold voltage. For this reason, the manufacturer selectively gives the high threshold voltage and the low threshold voltage to the memory cell transistors. If the threshold voltage is changed after the completion of the multi-layered wiring structure, the manufacturer can deliver the mask ROM devices within short time period.
The dopant concentration in the channel region determines the threshold voltage of the field effect transistor, and boron or phosphorous is ion implanted into the channel region.
FIGS. 1A
to
1
C illustrate the prior art process of fabricating an n-channel type field effect transistor. The prior art process shown in
FIGS. 1A
to
1
C is hereinbelow referred to as “first prior art process”. The threshold voltage of a field effect transistor is determined through a channel doping before formation of an inter-level insulating structure.
The first prior art process starts with preparation of a p-type silicon substrate
1
or a p-type well. A thick field oxide layer (not shown) is selectively grown on the major surface of the p-type silicon substrate
1
, and defines an active area assigned to the n-channel type field effect transistor. Boron is ion implanted into the active area, and forms a doped channel region
2
as shown in FIG.
1
A.
Subsequently, a surface portion of the active area is oxidized so as to cover the active area with a gate oxide layer
3
. Conductive material is deposited over the entire surface of the resultant structure, and the conductive layer is patterned into a gate electrode
4
. N-type dopant impurity is ion implanted into the active area, and forms lightly doped impurity regions (not shown) in a self-aligned manner with the gate electrode
4
. Insulating material is deposited over the entire surface of the resultant structure, and the insulating layer is etched without any etching mask. As a result, side wall spacers
5
are left on the side surfaces of the gate electrode
4
as shown in FIG.
1
B. N-type dopant impurity is ion implanted into the active area, and form heavily-doped impurity regions (not shown) in a self-aligned manner with the side wall spacers
5
. The heavily-doped impurity regions are nested in the lightly-doped impurity regions, and the heavily-doped impurity regions and the lightly-doped impurity regions form n-type source/drain regions (not shown). The doped channel region
2
, the gate insulating layer
3
, the gate electrode
4
, the side wall spacers
5
and the n-type source/drain regions as a whole constitute the n-channel type field effect transistor.
Subsequently, silicon oxide and boro-phosphosilicate glass are successively deposited over the entire surface of the resultant semiconductor structure, and form a silicon oxide layer
6
and a boro-phosphosilicate glass layer
7
over the n-channel type field effect transistor. The silicon oxide layer
6
and the boro-phosphosilicate glass layer
7
form in combination an inter-level insulating structure
8
.
Contact holes
8
a/
8
b
are formed in the inter-level insulating structure
8
, and the n-type source/drain regions are exposed to the contact holes
8
a/
8
b
, respectively. The contact holes
8
a
/
8
b
are plugged with conductive pieces
9
a/
9
b
, and conductive wiring strips
10
a/
10
b
are patterned on the inter-level insulating structure
8
as shown in FIG.
1
C. Thus, the dopant concentration in the channel region
2
is determined before completion of the inter-level insulating structure.
FIGS. 2A
to
2
C illustrate another prior art process, which is hereinbelow referred to as “second prior art process”. The threshold voltage of a field effect transistor is changed after completion of an inter-level insulating structure.
The second prior art process starts with preparation of a p-type silicon substrate
21
or a p-type well. A thick field oxide layer
22
is selectively grown on the major surface of the p-type silicon substrate
21
. A channel doping is carried out with boron for forming a doped channel region
22
, and lightly-doped impurity regions (not shown) and heavily-doped impurity regions (not shown) are formed in the self-aligned manner with the gate electrodes
24
on gate insulating layers
25
and side wall spacers
26
. A silicon oxide layer
27
and a boro-phosphosilicate glass layer
28
are deposited over the field effect transistors, and form in combination an inter-level insulating structure
29
. Contact holes
28
a
,
28
b
,
28
c
and
28
d
are formed in the interlevel insulating structure
29
, and the heavily-doped impurity regions are exposed to the contact holes
28
a
to
28
d
, respectively. The contact holes
28
a
to
28
d
are plugged with conductive pieces
30
a
,
30
b
,
30
c
and
30
d
as shown in FIG.
2
A.
A photo-resist ion-implantation mask
31
is formed on the inter-level insulating structure
29
, and is located over the right field effect transistor. Phosphorous is ion implanted into the doped channel region
23
uncovered with the photo-resist ion-implantation mask
31
at the dosage of 1×10
14
cm
−2
under acceleration energy of 1 MeV as shown in FIG.
2
B. The phosphorous is activated through an annealing at 800 degrees or higher than 800 degrees in centigrade. The phosphorous is concentrated into the doped channel region
23
a
, and cancels the effect of the boron ion implanted before the fabrication of the inter-level insulating structure
29
. The ion-implanted phosphorus lowers the threshold voltage of the left field effect transistor. Thus, the left field effect transistor has the low threshold voltage, and the right field effect transistor has the high threshold voltage. The ion-implantation at this stage is hereinbelow referred to as “second channel doping”.
Finally, conductive wiring strips
32
a
,
32
b
,
32
c
and
32
d
are patterned on the inter-level insulating structure
29
, and are held in contact with the conductive plugs
30
a
to
30
d
, respectively, as shown in FIG.
2
C.
The first prior art process encounters a problem in that the threshold
Chaudhari Chandra
Hutchins, Wheeler & Dittmar
NEC Corporation
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