Process for fabricating semiconductor device having semiconducto

Details Process for fabricating semiconductor device having semiconducto Process for fabricating semiconductor device having semiconducto

1997-11-20

1999-08-31

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438413, H01L 218242

Patent

active

059465700

ABSTRACT:
A memory cell of a semiconductor dynamic random access memory device requires a bit line contact hole open to a drain region of a cell transistor for connecting a bit line to the drain region and a node contact hole open to a source region for connecting a storage electrode of a stacked capacitor to the source region, and the bit line contact hole and the node contact hole are plugged with silicon layers; the silicon layers are epitaxially grown from the source and drain regions over an oxide-encapsulated gate electrode of the cell transistor so as to increase the contact areas; and the silicon layers are firstly anisotropically grown until reaching the upper surface of the oxide-encapsulated gate electrode, and, thereafter, isotropically grown so as to increase the contact areas.

REFERENCES:
patent: 5025741 (1991-06-01), Suwanai et al.
patent: 5030587 (1991-07-01), Wald et al.
patent: 5091330 (1992-02-01), Cambou et al.
patent: 5478768 (1995-12-01), Iwasa
patent: 5627094 (1997-05-01), Chan et al.
H. Hada et al., "A Self-Aligned Contact Technology Using Anisotropical Selective Epitaxial Silicon For Giga-Bit DRAMs", IEDM 95, 1995, pp. 665-668.

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