Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-28
2002-08-27
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S202000, C438S234000, C438S279000
Reexamination Certificate
active
06440802
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. 2000-257539 filed on Aug. 28, 2000, whose priority is claimed under 35 USC § 119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor device and, more particularly, to a process for fabricating a semiconductor device which has MOS transistors with and without drift diffusion regions on a single chip.
2. Description of the Related Art
In recent years, liquid crystal panels for use as displays of personal digital assistants such as portable phones have become higher in functionality and lower in costs. There have been correspondingly increasing demands for functionality enhancement and cost reduction of a liquid crystal driving device which is a principal part of such a liquid crystal panel.
The cost reduction of the liquid crystal panel is achieved by reduction in the number of components thereof.
An arrangement hitherto employed for the functionality enhancement is such that circuits for implementing necessary functions, e.g. a signal processing circuit and a memory circuit, are mounted in combination on the liquid crystal driving device.
More specifically, a plurality of multi-function circuits are mounted together on a chip formed with the liquid crystal driving device. Further, a higher level of integration is achieved through the size reduction of the liquid crystal driving device for prevention of the increase in chip size. In general, a chip having a plurality of multi-function circuits mounted thereon in addition to the liquid crystal driving device includes a low breakdown voltage section operative at a low voltage for ordinary signal processing and the like, and a high breakdown voltage section formed with a high breakdown voltage MOS transistor and the like operative at a high voltage for driving the liquid crystal and the like.
In the low breakdown voltage section, the impurity concentration in a well formed with a transistor should be set at a relatively high level for suppression of a short channel effect resulting from the size reduction.
In the high breakdown voltage section, on the other hand, the impurity concentration in a well should be set at a relatively low level to ensure a sufficient breakdown voltage. In particular, the high breakdown voltage MOS transistor typically has drift diffusion regions to alleviate the high voltage application to the transistor for prevention of the breakdown of the transistor itself.
Therefore, the fabrication of the chip having the low breakdown voltage section and the high breakdown voltage section requires the steps of forming masks respectively adapted for doping the low breakdown voltage section with an impurity in a high concentration, for doping the high breakdown voltage section with an impurity in a relatively low concentration, and for doping the drift diffusion regions of the high breakdown voltage MOS transistor with an impurity, and performing ion implantation with the use of the respective masks. In addition to these impurity doping steps, ion implantation is further needed for formation of device isolation regions, requiring an additional masking step. This results in a complicated fabrication process.
For simplification of the fabrication process, a technique has been proposed which employs a single mask for ion implantation for the formation of the drift diffusion regions of the high breakdown voltage MOS transistor and the device isolation regions (for example, Japanese Unexamined Patent Publication No. 1(1989)-157566).
In this method, a silicon oxide film
31
and a silicon nitride film
32
are formed over a P-type silicon substrate
30
preliminarily formed with an N-type well as shown in FIG.
6
(
a
). The silicon nitride film
32
is partly removed in regions where LOCOS oxide films are to be formed. A resist is applied over the resulting silicon substrate
30
, and openings are simultaneously formed in regions
34
which later serve as device isolation regions in a high breakdown voltage N-type transistor (HV-NTr) formation region, and in regions
35
which later serve as drift diffusion regions in a high breakdown voltage P-type transistor (HV-PTr) formation region. Thus, a resist pattern
33
is formed.
With the use of the resist pattern
33
thus formed, boron ions are implanted over the resulting substrate for formation of P-type diffusion layers
36
a
and
36
b
. In the regions
35
which later serve as the drift diffusion regions in the high breakdown voltage P-type transistor formation region, the boron ions are implanted into the surface of the silicon substrate
30
through the silicon nitride film
32
and the silicon oxide film
31
adapted for the LOCOS oxide film formation.
Thereafter, the LOCOS oxide films
37
are formed as shown in FIG.
6
(
b
). Thus, the P-type diffusion layers
36
a
of a relatively high boron concentration are located in the vicinity of interfaces between the LOCOS oxide films
37
and the silicon substrate
30
in the device isolation regions in the high breakdown voltage N-type transistor formation region, thereby allowing for device isolation. Further, the drift diffusion regions of the P-type diffusion layers
36
b
are located in the vicinity of the surface of the high breakdown voltage P-type transistor formation region.
Subsequently, drift diffusion regions
42
for the high breakdown voltage N-type transistor, gate oxide films
38
and gate electrodes
39
are formed on the resulting silicon substrate
30
, and then N
+
diffusion layers
40
and P
+
diffusion layers
41
are formed as source/drain regions in the resulting substrate. Thus, the high breakdown voltage P-type transistor HV-PTr and the high breakdown voltage N-type transistor HV-NTr are completed which each have the drift diffusion regions.
Such a fabrication process can simultaneously form the P-type diffusion layers
36
a
in the device isolation regions of the high breakdown voltage N-type transistor and the P-type diffusion layers
36
b
serving as the drift diffusion regions of the high breakdown voltage P-type transistor with the use of the single resist pattern. However, the segregation amount of the implanted impurity ions in the LOCOS oxide films is changed due to LOCOS oxidation variations and the like, because the ion implantation precedes the LOCOS oxidation. This causes variations in breakdown voltage in the device isolation regions, and increases variations in the sheet resistance and effective size of the drift diffusion regions, resulting in variations in the breakdown voltage of the resulting transistors.
To overcome this drawback, one conceivable approach is to implant ions into the silicon substrate under the LOCOS oxide films after the LOCOS oxidation. In this case, however, it is necessary to perform the ion implantation with an acceleration energy such that causes the ions to penetrate through the LOCOS oxide films. Therefore, an ion concentration peak in the drift diffusion region of the P-type diffusion layer
36
b
in the high breakdown voltage P-type transistor does not overlap an ion concentration peak in the P
+
diffusion layer
41
serving as the source/drain region to be formed later, as shown in
FIG. 7
, so that these regions are separated from each other. As a result, an electric field alleviation effect cannot be provided in an area A adjacent to the drain where the N-type well and the P+diffusion layer
41
contact each other. This leads to reduction in junction breakdown voltage, failing to protect the transistors from breakdown.
The aforesaid fabrication process requires two additional photolithography steps, because the low breakdown voltage section (not shown) should have an increased impurity concentration for suppression of the short channel effect and the high breakdown voltage section should have a relatively great junction depth and a relatively low impurity concentration to ensure a suffici
Hayashi Keiji
Nagata Masayuki
Luu Chuong A
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
Smith Matthew
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