Process for fabricating semiconductor device

Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S795000, C257SE21347

Reexamination Certificate

active

07932185

ABSTRACT:
A laser annealing process capable of suppressing a variation in sheet resistance. A surface layer formed shallower than 100 nm in a substrate of semiconductor material is added with impurities. The substrate is irradiated with a laser beam or its harmonic beam emitted from a laser diode pumped to solid-state laser to activate the impurities.

REFERENCES:
patent: 4370510 (1983-01-01), Stirn
patent: 4620785 (1986-11-01), Suzuki et al.
patent: 4655601 (1987-04-01), Suzuki
patent: 4694138 (1987-09-01), Oodaira et al.
patent: 5571430 (1996-11-01), Kawasaki et al.
patent: 5688715 (1997-11-01), Sexton et al.
patent: 5908307 (1999-06-01), Talwar et al.
patent: 5948287 (1999-09-01), Bandelin et al.
patent: 6297115 (2001-10-01), Yu
patent: 6472302 (2002-10-01), Lee
patent: 6475888 (2002-11-01), Sohn
patent: 6528397 (2003-03-01), Taketomi et al.
patent: 6566683 (2003-05-01), Ogawa et al.
patent: 6632729 (2003-10-01), Paton
patent: 6635588 (2003-10-01), Hawryluk et al.
patent: 6642122 (2003-11-01), Yu
patent: 6767773 (2004-07-01), Sano et al.
patent: 7432146 (2008-10-01), Yamamoto
patent: 2002/0086502 (2002-07-01), Liu et al.
patent: 2002/0121654 (2002-09-01), Yamamoto
patent: 2002/0175372 (2002-11-01), Takizawa
patent: 2003/0040130 (2003-02-01), Mayur et al.
patent: 2005/0224799 (2005-10-01), Yamamoto et al.
patent: 1049144 (2000-11-01), None
patent: 62104154 (1987-05-01), None
patent: 6322453 (1988-05-01), None
patent: 01187814 (1989-07-01), None
patent: 11-330463 (1999-11-01), None
patent: 11354463 (1999-12-01), None
patent: 2000260728 (2000-09-01), None
patent: 2000349039 (2000-12-01), None
patent: 2001-509316 (2001-07-01), None
patent: 2002-175772 (2002-06-01), None
patent: 2002-246601 (2002-08-01), None
patent: 2002-524846 (2002-08-01), None
patent: 2002-270505 (2002-09-01), None
patent: 2002-280548 (2002-09-01), None
patent: 2002261015 (2002-09-01), None
patent: 2002299346 (2002-10-01), None
patent: 2002343734 (2002-11-01), None
patent: 2003151906 (2003-05-01), None
patent: WO 98/33206 (1998-07-01), None
patent: WO 98/34268 (1998-08-01), None
patent: WO 00/13213 (2000-03-01), None
patent: WO 00/60655 (2000-10-01), None
patent: WO 01/80300 (2001-10-01), None
Murto et al, “An Investigation of Species Dependence in Germanium Pre-amorphized and Laser Thermal Annealed Ultra-Shallow Abrupt Junctions,” 2000 International Conference on Ion Implantation Technology Proceedings, IEEE, Sep. 17-22, 2000, pp. 182-185.
Murto et al, “Activation and Deactivation Studies of Laser Thermal Annealed Boron, Arsenic, Phosphorus, and Antimony Ultra-Shallow Abrupt Junctions,” 2000 International Conference on Ion Implantation Technology Proceedings, IEEE, Sep. 17-22, 2000, pp. 155-158.
Goto et al, “Ultra-Low Contact Resistance for Deca-nm MOSFETs by Laser Annealing,” IEDM Tech. Digest, 1999, pp. 931-933.
Yu et al, “70nm MOSFET with Ultra-Shallow, Abrupt, and Super-Doped S/D Extension Implemented by Laser Thermal Process (LTP),” IEDM Tech. Digest, 1999, p. 509.
Yamamoto et al, “Drive Current Enhancement by Ideal Junction Profile Using Laser Thermal Process,” Symposium on VLSI Technology Digest of Technical Papers, 2002, pp. 138-139.
Talwar et al, “Laser Thermal Processing (LTP) for Fabrication of Ultrashallow, Hyper-Abrupt, Highly Activated Junctions for Deca-Nanometer MOS Transistors,” Electrochemical Society Proceedings, Sep. 2000, pp. 95-105.
Park et al, “50 nm SOI CMOS Transistors with Ultra Shallow Junction Using Laser Annealing and Pre-Amorphization Implantation,” Symposium on VLSI Technology Digest of Technical Papers, 2001, pp. 69-70.
Yamamoto et al, “Impact of Pre-Amorphization for the Reduction of Contact Resistance Using Laser Thermal Process,” Extended Abstracts of International Workshop on Junction Technology, 2002, pp. 27-30.
Kagawa et al, “Influence of Pulse Duration on KrF Excimer Laser Annealing Process for Ultra Shallow Junction Formation,” Extended Abstracts of International Workshop on Junction Technology, 2002, pp. 31-34.
Kurobe et al, “Formation of Low-Resistive Ultra-Shallow n+/p Junction by Heat-Assisted Excimer Laser Annealing,” Extended Abstracts of International Workshop on Junction Technology, 2002, pp. 35-36.
Takashi Nire, “Ultra Shallow Junction Formation by Laser Anneal,” The Japan Society of Applied Physics, Silicon Technology Division, No. 39, 2002, pp. 23.-26.
European Search Report, PCT/JP2004007606, dated Apr. 23, 2008.
Japanese Office Action, Japanese Patent Application No. 2003-156769, Date of Completion: Apr. 19, 2010, Date Mailed: Apr. 27, 2010, pp. 1-3.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Process for fabricating semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for fabricating semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating semiconductor device will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2642429

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.