Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-01-28
2002-12-10
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S275000
Reexamination Certificate
active
06492230
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory and a process for fabricating the same, and more specifically to a nonvolatile semiconductor memory having a reduced chip area and a process for fabricating the same.
Referring to
FIG. 1
, there is shown a diagrammatic plan view illustrating a prior art nonvolatile semiconductor memory.
FIG. 2
is a diagrammatic sectional view taken along the line D—D in
FIG. 1
, and
FIGS. 3A and 3B
are views similar to that of
FIG. 2
but showing different problems in the prior art nonvolatile semiconductor memory.
In
FIGS. 1
,
2
,
3
A and
3
B, Reference Number
51
designates a floating gate of a memory cell in the nonvolatile semiconductor memory, and Reference Number
52
denotes a control gate formed above the floating gate
51
and functioning 'as a word line. Reference Number
53
indicates an insulating film between the floating gate
51
and the control gate
52
. Reference Numbers
54
and
55
show a drain and a source of the memory cell, respectively, and Reference Number
56
designates a channel region between the drain
54
and the source
55
. Thus, one memory cell is formed by the drain
54
, the source
55
, the channel region
56
between the drain
54
and the source
55
, and the floating gate
51
and the control gate
52
stacked above the channel region
56
, and each memory cell is isolated by a device isolation region
57
from adjacent memory cells.
Reference Number
61
indicates a selection transistor (selector) for selecting the memory cells. The selection transistor
61
is controlled by a selection signal line
62
functioning as a gate electrode.
The nonvolatile semiconductor memory thus formed includes a memory cell region in which a number of memory cells are formed and a selection transistor region in which a plurality of selection transistors are formed. The memory cell region is adjacent to the selection transistor region, but since the memory cells and the selection transistors cannot be formed in completely the same process, when the memory cells are formed, the selection transistor region is masked, and when the selection transistors are formed, the memory cell region is masked. Therefore, because of a misalignment of the mask, an unetched portion
64
remains at a boundary between the memory cell region and the selection transistor region, as shown in
FIG. 3A
, and in a later process, the unetched portion
64
collapses, with the result that the yield of production is deteriorated.
Alternatively, because of the misalignment of the mask, a substrate is overetched at the boundary between the memory cell region and the selection transistor region, as shown with Reference Number
65
in
FIG. 3B
by two etchings, one of which is performed for forming the memory cells, and the other of which is performed for forming the selection transistors.
In order to overcome the above problems, the prior art nonvolatile semiconductor memory was so constructed to have a dummy gate line
66
between the selection transistor region and the memory cell region, as shown in
FIGS. 1 and 2
. However, if the dummy gate line
66
is provided, the chip area of the nonvolatile semiconductor memory inevitably becomes increased.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a nonvolatile semiconductor memory which has overcome the above mentioned problem of the conventional prior art.
Another object of the present invention is to provide a nonvolatile semiconductor memory having a reduced chip area by making the dummy gate line unnecessary, and the process for fabricating the same.
Still another object of the present invention is to provide a nonvolatile semiconductor memory including the selection signal line having the function of the dummy gate line, thereby to reduce a necessary chip area, and the process for fabricating the same.
The above and other objects of the present invention are achieved in accordance with the present invention by a nonvolatile semiconductor memory comprising:
a memory cell region including a number of memory cells formed therein and each having a floating gate and a control gate formed above the floating gate, and a plurality of word lines extending in a first direction in parallel to each other, separately from each other; and
a selection transistor region positioned adjacent to the memory cell region and including one selection transistor formed therein and a selection signal line extending in parallel to the word lines;
wherein the selection signal line is formed on an inactive region in a substrate to extend in parallel to a boundary line between the memory cell region and the selection transistor region.
In an embodiment of the nonvolatile semiconductor memory, the inactive region includes a device isolation region formed in a principal surface of the substrate and a thick oxide film covering a diffused region formed in the principal surface of the substrate. For example, the selection signal line includes a layer which is formed of the same material as that of the control gate, and extends in parallel to the boundary line between the memory cell region and the selection transistor region, at a position retracting from the boundary line between the memory cell region and the selection transistor region.
According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory comprising:
a memory cell region including a number of memory cells formed therein and each having a floating gate and a control gate formed above the floating gate, and a plurality of word lines extending in a first direction in parallel to each other, separately from each other; and
a selection transistor region positioned adjacent to the memory cell region and including one selection transistor formed therein and a selection signal line extending in parallel to the word lines;
wherein the selection signal line includes a first layer which is formed of the same material as that of the floating gate and a second layer which is formed of the same material as that of the control gate.
Preferably, the selection signal line includes a short selection signal line extending therefrom in a second direction orthogonal to the first direction and going apart from the memory cell region, an end of the short selection signal line constituting a gate of the selection transistor.
In addition, the selection signal line includes a side surface extending on and along the boundary line between the memory cell region and the selection transistor region.
In a preferred embodiment, the selection signal line includes a short selection signal line extending therefrom in a second direction orthogonal to the first direction and going apart from the memory cell region, an end of the short selection signal line constituting a gate of the selection transistor.
According to a third aspect of the present invention, there is provided a process for fabricating a nonvolatile semiconductor memory which has a memory cell region including a number of memory cells formed therein and each having a floating gate and a control gate formed above the floating gate, and a plurality of word lines extending in a first direction in parallel to each other, separately from each other, and a selection transistor region positioned adjacent to the memory cell region and including one selection transistor formed therein and a selection signal line extending in parallel to the word lines, the processing comprising the steps of:
forming a device isolation film on a principal surface of a semiconductor substrate, forming a tunnel insulator film for the memory cells on the principal surface of the semiconductor substrate, forming a floating gate film on the tunnel insulator film, partially patterning the floating gate film, and forming source/drain regions at opposite sides of the partially patterned floating gate film by using the partially patterned floating gate film as a mask;
forming an oxide film to cover the whole surface of the s
Chaudhari Chandra
Young & Thompson
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