Process for fabricating multi-level read-only memory device

Details Process for fabricating multi-level read-only memory device Process for fabricating multi-level read-only memory device

1996-05-06

1997-09-16

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

H01L 21265

Patent

active

056680295

ABSTRACT:
A process for fabricating multi-level semiconductor ROM devices is disclosed. Each memory cell of the ROM device can be programmed to any of three possible conduction states including full-conduction, half-conduction and no-conduction. The fabrication process begins with a semiconductor silicon substrate. Buried bit and word lines are formed in the substrate. A photomask is then formed to correspond to code to be programmed into the ROM device. The photomask, when properly aligned over the ROM device, contains portions that fully cover the entire channel region of a cell to be programmed for full conduction, portions that partially cover the channel regions of cells that are to be programmed for half-conduction, and portions that do not cover at all the channel regions of cells to be programmed for no-conduction. Then ions are implanted with the photomask in place. The ions transform the regions not covered or partially covered by the photomask. In use, three levels of conduction current may then be sensed when the ROM device is accessed to represent three data levels.

REFERENCES:
patent: 5389565 (1995-02-01), Gyure et al.
patent: 5403764 (1995-04-01), Yamamoto et al.
patent: 5529942 (1996-06-01), Hong et al.
patent: 5536669 (1996-07-01), Su et al.

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