Process for fabricating memory cells with two levels of polysili

Details Process for fabricating memory cells with two levels of polysili Process for fabricating memory cells with two levels of polysili

1997-12-23

1999-11-16

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438290, H01L 218247

Patent

active

059857188

ABSTRACT:
A process for fabricating a memory cell having two levels of polysilicon and being included in a memory device of the EEPROM type, wherein the device is formed on a semiconductor material substrate which has a first conductivity type. The process comprises the steps of forming, on the substrate a thin tunnel oxide region surrounded by a gate oxide region previously formed on the same substrate, depositing a layer of polycrystalline silicon over the gate oxide region and the thin tunnel oxide region, and successively depositing a composite ONO layer and an additional polysilicon layer over the polycrystalline silicon layer. A capacitive implant mask having a window is formed by depositing a layer of a light-sensitive material over the additional polysilicon layer, a dopant is implanted through the window at an energy and with dosages effective to penetrate the polycrystalline silicon, ONO, and polysilicon layers, respectively, and a region of electric continuity is formed laterally and beneath the thin tunnel oxide region.

REFERENCES:
patent: 5607868 (1997-03-01), Chida et al.
patent: 5702957 (1997-12-01), Padmanabhan
patent: 5705416 (1998-01-01), Kim et al.
patent: 5789295 (1998-08-01), Liu
patent: 5877054 (1999-03-01), Yamauchi

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