Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-06-25
1998-06-02
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438594, H01L 218247
Patent
active
057598967
ABSTRACT:
A process for fabricating memory cells of flash memory devices that requires lower voltages between the drain and source regions when storing or erasing data, and avoids the punch-through problem associated with conventional flash memory devices having a high device density. The process includes forming successively on the surface of the silicon substrate a tunnel oxide layer, a floating gate layer, a dielectric layer, and a control gate layer. A portion of the tunnel oxide layer is exposed and unshielded. An ion implantation procedure is then applied to the silicon substrate to form a source region and a drain region. Sidewall spacers are then formed on the sidewalls of the control gate layer, the dielectric layer, the floating gate layer, and an unexposed portion of the tunnel oxide layer. Finally, an impurity is implanted by an inclined ion implantation procedure at incident angle of about 30 to 40 degrees to form a lightly-doped source region in the silicon substrate underneath the unshielded portion of the tunnel oxide layer.
REFERENCES:
patent: 5482879 (1996-01-01), Hong
patent: 5521109 (1996-05-01), Hsue et al.
Chaudhari Chandra
United Microelectronics Corporation
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