Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1994-02-10
1997-06-10
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438981, H01L 218247
Patent
active
056375204
ABSTRACT:
A process for simultaneously fabricating a flash-EEPROM memory and circuit transistors using a DPCC process. A first polysilicon layer is not removed from the circuit area, and the gate regions of a circuit transistors are formed by shorting first and second polysilicon layers. A thin tunnel oxide layer of the memory cells is formed using the same mask provided for implanting boron into the cell area of the substrate. Following implantation and without removing the mask, the gate oxide formed previously over the whole surface of the wafer is removed from the cell area; the boron implant mask is removed; and tunnel oxidation is performed to increase the thickness of the tunnel oxide by a desired amount, and to slightly increase the thickness of the oxide in the transistor area.
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Cantarelli Daniele
Cappelletti Paolo G.
Booth Richard A.
Morris James H.
Niebling John
SGS--Thomson Microelectronics S.r.l.
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