Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-21
2001-05-29
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S315000, C438S258000
Reexamination Certificate
active
06238979
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of electrically erasable programmable read only memory (EEPROM) devices. In particular, the present invention relates to a process for fabricating a EEPROM cell array which is embedded on core CMOS for analog applications.
BACKGROUND ART
Solid state memory is used to store digital bits (i.e., “1's and 0's) of data by means of semiconductor circuits. Solid state memory is classified as being either volatile memory or non-volatile memory. Volatile memory retains the digital bits of data only so long as power is applied and maintained to the circuits. For example, dynamic random access memory (DRAM) is often used in computer systems to temporarily store data as it is being processed by the microprocessor or CPU. Non-volatile memory, on the other hand, retains its digital bits of data, even after power has been shut off from the circuits. One common example of non-volatile memory is read-only memory (ROM). Some read-only memory can be programmed; these types of devices are known as programmable read-only memory (PROM). There exists a category of PROM devices which can be electrically erased so that they can actually be reprogrammed many times over to store different sets of data. These electrically erasable programmable read only memory are commonly referred to as EEPROMs.
EEPROM memory devices are typically comprised of an array of memory cells. Each individual memory cell can be programmed to store a single bit of data. The basic, fundamental challenge then in creating an EEPROM memory cell is to use a controllable and reproducible electrical effect which has enough nonlinearity so that the memory cell can be written or erased at one voltage in less than 1 ms and can be read at another voltage, without any change in the programmed data for more than 10 years.
Fowler-Nordheim tunneling, which was first described by Fowler and Nordheim in 1928, exhibits the required nonlinearity and has been widely used in EEPROM memories. Due to the unique physical properties of silicon (Si), the energy difference between the conduction band and the valence band is 1.1 eV. In silicon dioxide (SiO
2
), the energy difference between these bands is about 8.1 eV, with the conduction band in SiO
2
3.2 eV above that in Si. Since electron energy is about 0.025 eV at thermal room temperature, the probability that an electron in Si can gain enough thermal energy to surmount the Si-to- SiO
2
barrier and enter the conduction band in SiO
2
is very small. Thereby, if electrons are placed on a polysilicon floating gate surrounded by SiO
2
, then this band diagram will by itself insure the retention of data.
By taking advantage of this Fowler-Nordheim tunneling principle, a specific EEPROM memory cell, typically comprised of a single transistor, can be addressably programmed by applying electrical signals to a specified row and a specified column of the memory array matrix. For example, to write a logic “1” or a logic “0” into a memory cell, a voltage is applied to the control gate corresponding to the row (word line) of the selected cell, while a voltage corresponding to either a “1” or a “0” is applied to the source or drain corresponding to the column (bit line) of the selected cell. At the same time, other memory cells are prevented from being written to by applying specific voltages to their word and bit lines such that they become write inhibited. Likewise, particular memory cells can be erased while others are prevented from being erased (erase inhibited) by applying the appropriate voltages to the designated word and bit lines. By selectively applying voltages to the word and bit lines, memory cells can be read from, written to, write inhibited, erased, and erase inhibited.
As the design of EEPROM cells evolved, it has become possible to pack more and more memory cells into a single EEPROM chip. However, the increased density and efficiency of EEPROM cells has come at the expense of complexity.
FIG. 1
shows an exemplary prior art EEPROM cell. It is described in the U.S. Pat. No. 5,379,253 “High Density EEPROM Cell Array With Novel Programming Scheme And Method Of Manufacture,” issued to inventor Albert Bergemont, Jan. 3, 1995. It can be seen that this EEPROM cell design call for the use of multiple layers, including multiple polysilicon layers. Each additional layer dramatically increases the complexity for fabricating such a EEPROM cell. Although the complexity of a single memory cell has increased, scaling this memory cell design across a huge array has proven to be quite profitable because the memory needs of many applications necessitate the use of dedicated, high density EEPROM chips.
Sometimes though, EEPROM cells are used in analog applications, such as in trimming capacitors, resistors, etc. Utilizing a traditional EEPROM cell in these types of core CMOS analog applications is not cost-efficient. This is because the state-of-the-art EEPROM cell layout and structure has been optimized for stand-alone EEPROM chips. It is extremely difficult to embed these stand-alone EEPROM cells for use on core CMOS analog applications due to the complexity to fabricate them. Conventional stand alone EEPROM cell designs typically involved having a double polysilicon process with high voltage enhancement and depletion transistors. As such, they are not ideally suited for limited use in certain analog applications.
Thus, there exists a need in the prior art for a cost-effective EEPROM cell solution which can readily be embedded on core CMOS for analog applications. The present invention provides a process for fabricating low cost, full feature EEPROM cells which satisfy this need.
SUMMARY OF THE INVENTION
The present invention pertains to a process of fabricating an electrically erasable programmable read only memory cell embedded on core complementary metal oxide silicon for analog applications. First, a P-well region is formed. Two spaced-apart N-well regions are formed within the P-well. A first field oxide layer is deposited over the P-well and two N-wells. A high-voltage oxide layer is then grown over the first field oxide layer. A first photoresist mask which defines a tunneling window is then overlaid. The first field oxide layer and the high-voltage oxide layer are then etched. Afterwards, the first photoresist mask is stripped away. A tunnel oxide layer is grown. A polysilicon layer is grown on top of the tunnel oxide layer and doped. A second photoresist mask which defines a floating gate is overlaid on top of the polysilicon layer. The polysilicon layer is then etched, and the second photoresist mask is stripped away. Thereby, only a single polysilicon layer and masking step is required to manufacture the embedded EEPROM memory cell according to the present invention.
In one embodiment, the process can be used to fabricate an array of at least four EEPROM memory cells. This is accomplished by utilizing an N-well mask having at least three regions which defines a first N-well region, a second N-well region, and a third N-well region. The first N-well region and the third N-well region act as coupling areas and the second N-well region acts as tunnel window regions for the EEPROM memory cell array. A first photoresist mask defines at least four tunnel window regions, one tunnel window region in each of four P+ regions residing within the second N-well. The second photoresist mask defines at least four T-shaped floating gates corresponding to four EEPROM cells, wherein each of the floating gates extends from one tunneling window residing within one N-well to another N-well. Furthermore, the second photoresist mask also defines one or more high-voltage transistors. Additionally, logic gates may be fabricated over the EEPROM memory cell array by mask protecting the EEPROM memory cells and then depositing an oxide layer.
REFERENCES:
patent: 5498560 (1996-03-01), Sharma et al.
patent: 6043123 (2000-03-01), Wang et al.
patent: 6071778 (2000-06-01), Bez et al.
Booth Richard
National Semiconductor Corporation
Wagner , Murabito & Hao LLP
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