Process for fabricating bitlines

Details Process for fabricating bitlines Process for fabricating bitlines

1998-03-03

1999-11-09

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438253, 438647, 438648, 438649, 438666, 438256, H01L 218242

Patent

active

059813300

ABSTRACT:
A process for fabricating bitlines for DRAM devices having improved bitline electrical contact is disclosed. Good electrical connection for the bitline in its contact opening is secured by forming a contact interface utilizing titanium silicide. The process includes first forming contact openings revealing the source/drain regions of the transistor of the cell units followed by the formation of a polysilicon layer filling into the openings and contacting the revealed surface of the transistor source/drain regions. A tungsten silicide layer then covers the polysilicon layer, with a titanium layer further covering the tungsten silicide layer, and the polysilicon layer in the contact opening exposed out of coverage by the tungsten silicide layer due to insufficient step coverage of the tungsten silicide layer in the openings. A titanium nitride layer then covers the titanium layer, with a titanium silicide layer interfacing between the polysilicon layer and the tungsten silicide filled inside the openings.

REFERENCES:
patent: 5231052 (1993-07-01), Lu et al.
patent: 5565708 (1996-10-01), Ohsaki et al.

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