Process for fabricating an EEPROM

Details Process for fabricating an EEPROM Process for fabricating an EEPROM

1998-11-02

2001-08-21

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S265000

Reexamination Certificate

active

06277692

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to EEPROM devices, and more particularly to an improved process for fabricating an EEPROM that protects a sensitive tunnel dielectric area from contamination resulting from subsequent processing steps.
BRIEF DESCRIPTION OF THE PRIOR ART
An electrically erasable and electrically programmable memory cell EEPROM is disclosed in U.S. Pat. No. 4,115,915 by Harari, and in U.S. Pat. No. 4,203,158 by Frohman-Bentchkowsky et al. An improved EEPROM is disclosed in U.S. Pat. No. 5,021,848 by Chiu, wherein the EEPROM tunnel dielectric area has the benefit of being very small and self aligned with the floating gate.
EEPROM devices are now being produced in high volume. The cost of EEPROMs is influenced by production yields and related inspection processes, as well as other production cost parameters. In semiconductor processing, the reduction of contamination of material is always an important issue. Environmental contaminants during process steps, and the influence of subsequent processes on earlier processing results is a concern in need of constant attention.
There is, therefore, a need for improved processing methods that minimize the possibility of wafer contamination during the processing steps of manufacturing electrically-erasable and electrically programmable memory storage devices, i.e. EEPROMs.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an improved method of manufacturing EEPROMs that reduces the possibility of wafer contamination.
It is a further object of the present invention to provide a method of sealing the processed EEPROM tunnel dielectric area from contamination resulting from subsequent processing steps.
Briefly, a preferred embodiment of the present invention includes method steps in the fabrication of EEPROM memory cell and cell selection devices after formation of a poly
1
floating gate, including first implanting a P-type substrate with an N-type impurity to form a buried N+ junction, and then growing a first thin oxide layer over the buried N+ junction and on sidewalls of the memory cell poly
1
floating gate and a selection device gate. The method steps of the preferred embodiment are for protection of the first thin oxide layer including a tunnel dielectric while forming an add-on Poly Si gate horizontally adjacent to the selection device gate, and an add-on gate adjacent the poly
1
floating gate and vertically above the buried N+ junction, the junction separated from the poly
1
floating gate by the first thin oxide layer at the base of the poly
1
floating gate. The method continues by depositing a thin layer of polysilicon and then growing a second thin oxide layer over the thin polysilicon layer. A photoresist is applied, and then removed from the top surface and the sidewalls of the poly
1
floating gate structures. With the photoresist protecting the second thin oxide layer, and the thin layer of polysilicon protecting the tunnel dielectric portion of the first thin oxide area over the buried N+ junction, the second thin oxide on the thin polysilicon layer is removed from the top surface and the vertical sidewalls of the poly
1
floating gate structures. The photoresist is removed, and the thin poly silicon layer is removed from the sidewalls and top of the poly
1
floating gate structure. Then, the second thin oxide on the thin poly silicon over the Buried N+ junction and the first thin oxide on the sidewalls of the poly
1
floating gate structures are removed. With the tunnel dielectric area thus protected, an add-on polysilicon layer is deposited and etched back to form the add-on floating gate at the sidewalls of the floating gate of the memory cell, and the add-on gate to the selection device.
An advantage of the present invention is that it provides protection of a tunnel dielectric area during formation of add-on gates.
A further advantage of the present invention is that it increases the production yield of EEPROM devices.


REFERENCES:
patent: 4115915 (1978-09-01), Harari
patent: 4203158 (1980-05-01), Bentchkowsky et al.
patent: 5021848 (1991-06-01), Chiu
patent: 5470773 (1995-11-01), Liu et al.
patent: 5840607 (1998-11-01), Yeh et al.

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