Process for fabricating a semiconductor integrated circuit devic

Details Process for fabricating a semiconductor integrated circuit devic Process for fabricating a semiconductor integrated circuit devic

1995-03-27

1997-08-26

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438397, H01L 2170, H01L 2700

Patent

active

056610610

ABSTRACT:
A process for forming an upper-layer fin and a lower-layer fin of a storage electrode, and a semiconductor integrated circuit device fabricated by the process. When two-layered polycrystalline silicon films are to be sequentially etched to form the upper-layer fin and the lower-layer fin by the dry-etching method using a first mask, the upper polycrystalline silicon film is patterned at first so far as to form the clearance of the upper-layer fins with the minimum working size of the memory cells of a DRAM, to form the upper-layer fin. Next, the lower-layer fin is formed by the dry-etching method using a second mask which has a pattern enlarged in self-alignment from the pattern of the first mask, so that it is given a larger horizontal size than that of the upper-layer fin.

REFERENCES:
patent: 5273925 (1993-12-01), Yamanaka
patent: 5290726 (1994-03-01), Kim
patent: 5336638 (1994-08-01), Suzuki et al.

Affiliated with

Also associated with

Rating

Process for fabricating a semiconductor integrated circuit devic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for fabricating a semiconductor integrated circuit devic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating a semiconductor integrated circuit devic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1987814