Process for fabricating a semiconductor device including a nonvo

Details Process for fabricating a semiconductor device including a nonvo Process for fabricating a semiconductor device including a nonvo

1996-05-22

2000-01-25

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438593, 438594, 257316, 257318, 257321, H01L 21336

Patent

active

060177926

ABSTRACT:
A nonvolatile memory device includes a floating-gate electrode (14) overlying a surface (24) of a substrate (10). A diffusion barrier layer (34) extends from the substrate surface (24) along a wall surface (30) of the floating-gate electrode (14) to an upper surface (32) of the floating-gate electrode (14) and overlies the upper surface (32). The diffusion barrier layer (34) blocks the silicidation of the floating-gate electrode (14) and prevents ionic contaminants from diffusing to the floating-gate electrode (14). A charge control region (42) of the floating-gate electrode (14) is capacitively coupled to a well region (40) within the substrate (10). The well region (40) functions as a diffused control-gate electrode and regulates the voltage of the floating-gate electrode (14).

REFERENCES:
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patent: 5453634 (1995-09-01), Mori
patent: 5457335 (1995-10-01), Kuroda et al.
Yoshikawa et al.; "An EPROM Cell Struction for EPLD's Compatible with Single Poly-Si Gate Process;" IEEE Trans. on Electron Devices; vol. 37, No. 3; pp. 675-679 (1990).
Wolf et al.; Silicon Processing for the VLSI Era; vol. 1: Process Technology; Lattice Press; p. 385 (1986).
Krakauer et al.; "ESD Protection in a 3.3 V Sub-Micron Silicided CMOS Technology;" EOS/ESD Symposium Proceedings--1992; pp. 250-257 (1992).

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