Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Utility Patent
2000-01-19
2001-01-02
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S527000
Utility Patent
active
06168993
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
Related subject matter is disclosed in co-pending, commonly assigned patent application, “PROCESS FOR FABRICATING AN EEPROM DEVICE HAVING A POCKET SUBSTRATE REGION,” filed on even date herewith.
FIELD OF THE INVENTION
This invention relates, generally, to a process for fabricating semiconductor devices and, more particularly, to processes for fabricating multiple doped regions in semiconductor devices, such as pocket regions in EEPROM devices.
BACKGROUND OF THE INVENTION
During semiconductor fabrication, numerous doped regions are formed in a semiconductor substrate. These doped regions perform various functions, such as source and drain regions for metal-oxide-semiconductor (MOS) transistors, buried electrical signal lines, substrate resistors and the like. Often, it is necessary to form doped regions having varying junction depths in order to meet the different electrical resistance requirements and current handling requirements of a semiconductor device. Because of the electrical field created by a buried junction, the geometric profile of the junction can be important where electric components having extremely small feature size are being fabricated. For example, a lightly-doped-drain (LDD) structure in the channel region of an MOS transistor are necessary to insure proper functioning of a sub-micron transistor. Additionally, in advanced electrically-erasable-programmable-read-only-memory (EEPROM) devices, pocket regions must be fabricated in a semiconductor substrate having a precise junction profile within the substrate.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. EEPROM device designers have taken advantage of the ability of silicon nitride to store charge in localized regions and have designed memory circuits that utilize two regions of stored charge within an oxide-nitride-oxide (ONO) layer. This type of non-volatile memory device is known as a two-bit EEPROM. The two-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left and right bit is stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell. Programming methods are then used that enable two-bits to be programmed and read simultaneously. The two-bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions. The two-bit memory cell requires pocket regions adjacent to a buries bit-line region. Electrons are sourced from the pocket regions and injected into the silicon nitride layer.
As advanced MOS and EEPROM devices are scaled to smaller dimensions, it becomes more difficult to form the doped regions at precise locations in the substrate. In particular, the pocket regions of EEPROM arrays using two-bit data storage and the LDD regions of MOS transistors must be carefully fabricated to avoid excessive overlap with the source and drain regions. Accordingly, as device dimensions are scaled to smaller values, advances in fabrication technology are necessary to insure proper functioning devices.
BRIEF SUMMARY OF THE INVENTION
A process for fabricating a semiconductor device advantageously enables the formation of a graded junction in a semiconductor substrate. In particular, the process of the invention can be used for the formation of pocket regions in an EEPROM device by carrying out a doping step at an angle of incidence normal to the substrate surface. The ability to form pocket regions at normal angles of incidence enables the formation of pocket regions having precisely determined junction profiles. Additionally, the pocket regions, in combination with a buried bit-line region, create a graded junction within the semiconductor substrate. Improved functionality in EEPROM devices is realized by forming a graded junction in the bit-line region in accordance with the present invention.
In one form, the process of the present invention includes providing a semiconductor substrate having a principal surface. A patterned resist layer is formed overlying the principal surface. The patterned resist layer has a substantially vertical edge surface. The semiconductor substrate is doped using the patterned resist layer to form a first doped region in the substrate. The first doped region has a junction profile substantially continuous with the first substantially vertical edge surface. The patterned resist layer is then processed to form a second substantially vertical edge surface, which is laterally displaced from the first substantially vertical edge surface. A portion of the principal surface of the semiconductor substrate separates the first substantially vertical edge surface from the second substantially vertical edge surface. The patterned resist layer is then used to form a second doped region in the substrate. The second doped region has a junction profile substantially continuous with the second substantially vertical edge surface.
REFERENCES:
patent: 3997367 (1976-12-01), Yau
patent: 4818715 (1989-04-01), Chao
patent: 4837180 (1989-06-01), Chao
Foote David K.
Kluth George
Rangarajan Bharath
Wang Fei
Advanced Micro Devices , Inc.
Booth Richard
Brinks Hofer Gilson & Lione
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