Process for fabricating a semiconductor device component...

Details Process for fabricating a semiconductor device component... Process for fabricating a semiconductor device component...

1999-04-12

2001-04-10

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S265000, C438S299000, C438S431000, C438S595000, C438S634000

Reexamination Certificate

active

06214683

ABSTRACT:

REFERENCE TO RELATED APPLICATIONS
Related subject matter is disclosed in the following commonly-assigned, co-pending patent applications filed on even date herewith:
APPLICATION
TITLE
SER. NO.
PROCESS FOR FABRICATING A
09/290,088
SEMICONDUCTOR DEVICE COMPONENT BY
OXIDIZING A SILICON HARD MASK
PROCESS FOR FABRICATING A
09/290,087
SEMICONDUCTOR DEVICE COMPONENT USING
A SELECTIVE SILICIDTION REACTION
PROCESS FOR FABRICATING A METAL
09/290,086
SEMICONDUCTOR DEVICE COMPONENT BY
LATERAL OXIDATION
FIELD OF THE INVENTION
This invention relates, in general, to semiconductor device fabrication, and more particularly, to the fabrication of MOS transistors having sub-micron dimensions.
BACKGROUND OF THE INVENTION
There is a continuing trend in the semiconductor industry to fabricate integrated circuits of increasing complexity. As the complexity of an integrated circuit increases, the cost associated with fabricating the integrated circuit also increase. In order to provide integrated circuit devices having increased functional capability, while maintaining control over the cost associated with fabrication, more devices must be included on each semiconductor wafer. In recent years, integrated circuit fabrication technology has achieved the ability to define circuit components having feature sizes in the sub-microns size range. For example, new lithographic techniques have been developed using x-ray and deep UV energy sources. Additionally, film deposition technology now exist that can form thin-films having a precisely determined metallurgical composition and thickness. Furthermore, thin-film etching techniques have been developed which are capable of selectively etching one metallurgical composition, while not substantially etching other metallurgical compositions present on the semiconductor substrate.
However, even with the marked advances in fabrication technology, achievement of the necessary packing density and cost control in the manufacture of modern integrated circuits requires further processing innovations. This is because as device dimensions, such as the length of gate electrodes in metal-oxide-semiconductor (MOS) transistors, continue to be scaled to smaller dimensions new physical process limitations arise.
One major impediment to further size reduction of MOS transistors relates to the physical limitation of lithographic technology. Photolithographic techniques utilize an optically sensitive resist material that is formed on a semiconductor substrate. A photolithographic mask having a predetermined pattern is aligned to the semiconductor wafer and light is passed through the mask. After exposing the resist, the resist is developed to form a pattern on the wafer. The photoresist exposure steps typically require a difficult alignment of the mask with the wafer. In addition to alignment difficulty, the smallest feature size that can be photolithographically defined is limited by optical detraction. To reduce the amount of defraction in lithographic operations, manufacturers have resorted to the use of deep UV lithographic techniques to overcome some of the diffraction problems encountered using higher wave lengths of light. However, even deep UV lithography is not able to reliably define feature sizes of 0.1 microns and smaller.
To further enhance the performance of lithographic technology, manufacturers have developed advanced resist materials and coatings, such as antireflective coatings, and the like, to improve the ability of optical lithography to produce sub-micron features. Additionally, post-feature definition methods, such as photoresist trimming, are also used to reduce the feature size to dimensions below the photolithographic limit. Although advances in resist materials and processing methods have extended the limit of lithography to smaller dimensions, the precise formation of extremely small feature sizes remains beyond the ability of present process technology.
The fabrication of MOS transistors to have gate electrodes on the order of 0.1 microns requires processing technology beyond existing lithographic and resist formulation technologies. In many ways, the smallest feature size to which an MOS gate electrode can be fabricated governs the scaling of all other device components in an integrated circuit. The feature size of an MOS gate electrode must be continuously scaled down to improve the performance and operational capabilities of an integrated circuit. Accordingly, an improved fabrication process is necessary to reliably manufacture device components, such as MOS transistors having gate lengths on the order of 0.1 microns and smaller.
SUMMARY OF THE INVENTION
The present invention is for a process of fabricating a semiconductor device having feature sizes that are independent of lithographic limitations. In one embodiment, the process of the invention is advantageously used to fabricate the gate electrode of an MOS transistor. The lateral dimensions of the MOS gate electrode are initially defined by a lithographic process. However, the final lateral dimensions of the gate electrode are defined by laterally oxidizing portions of a hard-mask overlying the gate-forming layer. Once the oxidized portions are removed, the remaining unoxidized portion becomes the masking layer for the formation of the gate electrode. The process of the invention advantageously enables features on semiconductor devices to be fabricated to extremely small lateral dimensions, regardless of the capability of the lithographic system.
In one form, a semiconductor substrate is provided having a device component layer thereon. An etch-stop layer is formed to overlie the device component layer, and an oxidizable layer is formed to overlie the etch-stop layer. Then, an oxidation resistant layer is formed to overlie the oxidizable layer. The oxidation resistant layer and the oxidizable layer are processed to form a hard-mask having a first length. An oxidation process is then carried out to laterally oxidize the oxidizable layer leaving a residual layer having a second length. The second length is less than the first length. Following the oxidation process, the oxidation resistant layer is removed and the etch-stop layer and the device component layer are sequentially etched using the residual layer as an etching mask.


REFERENCES:
patent: 5837588 (1998-11-01), Wu
patent: 5866473 (1999-02-01), Xiang et al.
patent: 6046090 (1998-11-01), Wu

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