Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-02-15
2002-11-12
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S678000, C438S686000
Reexamination Certificate
active
06479384
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor device. More particularly, the present invention is concerned with a process for fabricating a semiconductor device using a trench wiring technique, such as a dual Damascene process or a single Damascene process.
2. Related Art
As a material for wirings in large scale integrated-circuits (LSIs), an aluminum alloy has conventionally been used. As strong demands for LSI's which are further reduced in size and exhibit high speed increase, the wiring made of an aluminum alloy is difficult to meet such demands and secure a satisfactory performance (high reliability and low resistance). As a method for solving this problem, attention is drawn to a technique for forming a wiring from copper which has an excellent resistance to electromigration and a low resistance, as compared to the aluminum alloy, and studies are being made with a view toward putting this technique into practical use.
Generally, copper is not easily dry-etched. Therefore, in the formation of a copper wiring, a process of forming a trench wiring is promising. The trench wiring is produced by a process in which a predetermined trench is preliminarily formed in an interlayer dielectric comprised of, for example, silicon oxide, and the trench is plugged with a wiring material. Then, the excess wiring material is removed by, for example, a chemical mechanical polishing (hereinafter, frequently referred to simply as “CMP”) process, to thereby form a wiring in the trench.
The copper wiring is generally used in the form of a multilayer wiring. When such a multilayer copper wiring is formed, no barrier film which prevents copper from diffusing is present on the surface of the copper wiring. Therefore, before an upper layer wiring is formed on the copper wiring, as a diffusion-preventing film for copper, a barrier film comprised of silicon nitride, carbon nitride or the like is formed on the copper wiring. Silicon nitride and carbon nitride have a relative dielectric constant larger than that of silicon oxide. Therefore, it is considered that these are advantageous in a method in which the surface of copper after the CMP process is selectively coated with these. In addition, U.S. Pat. No. 5,695,810 discloses a method in which the surface of copper is coated with a cobalt tungsten phosphorus (CoWP) film. In this method, cobalt tungsten phosphorus is deposited by an electroless plating method using the surface of copper as a catalyst.
Further, Japanese Patent Application Laid-Open Specification No. 9-307234 (which is one of basic applications of U.S. Pat. No. 5,830,563) discloses a method used in a printed-wiring substrate, in which the exposed copper surface is subjected to palladium displacement plating, and electroless plating is conducted using the displaced palladium as a catalyst nucleus. On the other hand, as a catalyst activation treatment for electroless plating, a method in which palladium ions are reduced utilizing an oxidation reaction of tin ions, a method using a palladium sol, a method using a silane coupling agent, and the like are known.
However, the catalytic activity of copper is lower than that of gold (Au), nickel (Ni), palladium (Pd), cobalt (Co) or platinum (Pt). Therefore, in the electroless plating method using a hypophosphite as a reducing agent, when a metal having an ionization tendency larger than that of copper is electroless-plated on copper, a unfavorable phenomenon such that plating cannot be conducted at all, the plating cannot be conducted uniformly, the plating rate is low, or the like is likely to occur.
In addition, as shown in
FIG. 3A
, in the palladium catalyst method used in a general electroless plating method, it is known that palladium
131
is formed in an island form on the entire surface of both a copper wiring
121
and an interlayer dielectric film
111
. In this case, as shown in
FIG. 3B
, a barrier layer
131
comprised of cobalt tungsten phosphorus is formed by plating using, as a catalyst nucleus, the palladium formed in an island form on the entire surface of both the copper wiring
121
and the interlayer dielectric film
111
. However, palladium is ununiformly formed. Therefore, the barrier layer
131
, which grows using such palladium as a nucleus, is likely to be also an ununiform film. In addition, for forming the barrier layer
131
in the form of a so-called continuous film on the entire surface of both the copper wiring
121
and the interlayer dielectric film
111
, it is necessary to increase the thickness of the barrier layer, and the thickness depends on the density of the palladium formed in an island form. Such problems make it difficult to control the process.
Further, in the conventional palladium catalyst method, it is difficult to selectively form a palladium catalyst layer on the copper wiring, and thus, palladium elements disadvantageously adsorb onto the entire surface to be treated. In addition, in the palladium catalyst method using tin ions, it is confirmed that tin elements are drawn into the palladium layer, and problems are encountered in that tin causes the wiring resistance to rise and the long-term reliability of the wiring to be poor.
SUMMARY OF THE INVENTION
In this situation, the present inventors have made extensive and intensive studies with a view toward solving the above-mentioned problems accompanying the prior art, in connection with the process for fabricating a semiconductor device, which comprises forming, on a metal wiring formed from copper or a copper alloy, a barrier film which functions as a diffusion-preventing film for the metal wiring by an electroless plating method. As a result, it has unexpectedly been found that the above-mentioned problems inevitably accompanying the conventional techniques can be solved by, on the metal wiring, selectively forming a catalytic metal film which serves as a catalyst in the electroless plating method by a displacement plating method using a displacement plating solution at a temperature in a range of 30° C. or more and lower than a boiling point thereof; and selectively forming the barrier film on the catalytic metal film by the electroless plating method. The present invention has been completed, based on the above novel finding.
According to the above-described process for fabricating a semiconductor device, it is possible to uniformly form the catalytic metal film on the metal wiring since the catalytic metal film, which reacts as a catalyst for electroless plating, is selectively formed on the metal wiring by the displacement plating using the displacement plating solution at a temperature in the range of 30° C. or more and lower than a boiling point thereof. On the other hand, in a case where the temperature of the displacement plating solution is lower 30° C., the catalyst metal tend not to be deposited. Accordingly, it is difficult to form a uniform catalytic metal film on the metal wiring. In addition, in a case where the temperature of the displacement plating solution is higher than the boiling point thereof, gasification occurs in the displacement plating solution and the solution is difficult to be kept static. Or, gasification may continuously occur on a part of the metal wiring. Therefore, the temperature of the displacement plating solution is set to be in the range of 30° C. or more and lower than the boiling point thereof.
The pH of the displacement plating solution is need to be set in a range of 0.5 to 2.5, more preferably, 0.5 to 2.0. If the pH of the displacement plating solution is not adjusted appropriately, for example, the pH of the displacement plating solution is lower than 0.5, it becomes easy for the catalytic metal to physically absorb even on the surface other than the metal wiring, and thus, it becomes difficult to carry out the selective displacement plating. In a case where the pH of the displacement plating solution is higher than 2.5, the deposition speed of the catalytic metal becomes low and the catalytic metal is har
Komai Naoki
Nogami Takeshi
Segawa Yuji
Nguyen Thanh
Nguyen Tuan H.
Sonnenschein Nath & Rosenthal
Sony Corporation
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