Process for fabricating a self-aligned deposited...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S299000, C438S300000

Reexamination Certificate

active

07902029

ABSTRACT:
Processes for forming self-aligned, deposited source/drain, insulated gate, transistors and, in particular, FETs. By depositing a source/drain in a recess such that it remains only in the recess, the source/drain can be formed self-aligned to a gate and/or a channel of such a device. For example, in one such process a gate structure of a transistor may be formed and, in a material surrounding the gate structure, a recess created so as to be aligned to an edge of the gate structure. Subsequently, a source/drain conducting material may be deposited in the recess. Such a source/drain conducting material may be deposited, in some cases, as layers, with one or more such layers being planarized following its deposition. In this way, the conducting material is kept within the boundaries of the recess.

REFERENCES:
patent: 3590471 (1971-07-01), Lepselter et al.
patent: 3708360 (1973-01-01), Wakefield, Jr. et al.
patent: 3983264 (1976-09-01), Schroen et al.
patent: 4056642 (1977-11-01), Saxena et al.
patent: 4300152 (1981-11-01), Lepselter
patent: 4485550 (1984-12-01), Koeneke et al.
patent: 5021365 (1991-06-01), Kirchner et al.
patent: 5399206 (1995-03-01), de Lyon
patent: 5578848 (1996-11-01), Kwong et al.
patent: 5596218 (1997-01-01), Soleimani et al.
patent: 5612567 (1997-03-01), Baliga
patent: 5663584 (1997-09-01), Welch
patent: 5801398 (1998-09-01), Hebiguchi
patent: 5888891 (1999-03-01), Gould
patent: 5939763 (1999-08-01), Hao et al.
patent: 5943575 (1999-08-01), Chung et al.
patent: 6037605 (2000-03-01), Yoshimura
patent: 6091076 (2000-07-01), Deleonibus et al.
patent: 6096590 (2000-08-01), Chan et al.
patent: 6150286 (2000-11-01), Sun et al.
patent: 6198113 (2001-03-01), Grupp
patent: 6207976 (2001-03-01), Takshashi et al.
patent: 6261932 (2001-07-01), Hulfachor
patent: 6291866 (2001-09-01), Wallace et al.
patent: 6291867 (2001-09-01), Wallace et al.
patent: 6303479 (2001-10-01), Snyder
patent: 6958500 (2005-10-01), Saito
patent: 6982460 (2006-01-01), Cohen et al.
patent: 7238985 (2007-07-01), Jones et al.
patent: 2004/0142524 (2004-07-01), Grupp et al.
patent: 2006/0214236 (2006-09-01), Chien
patent: 0295490 (1988-12-01), None
patent: 0789388 (1997-08-01), None
Acorn Technologies, Inc., International Search Report and Written Opinion, Mar. 2, 2006, 8 pp.
Aberle, Armin G., et al., “Injection-Level Dependent Surface Recombination Velocities at The Silicon-Plasma Silicon Nitrite Interface”,Institut fur Solaernergieforschung, ISFH, D-3 1860 Emmerthal, Germany, (Mar. 9, 1995), pp. 2828-2830.
B. J. Zhang, et al., “Schottky Diodes of Ni/Au on n-GaN Grown on Sapphire and SiC Substrates”,Applied Physics Letters, vol. 79, No. 16, (Oct. 15, 2001), pp. 2567-2569.
B.R. Weinberger, et al., “Surface Chemistry of HF Passivation Silicon: X-Ray Photoelectron And Lon Scattering Spectroscopy Results”,J. Appl. Phys. 60(9), (11/186), pp. 3232-3234.
Blosse, A., et al., “A Novel Low Cost 65nm CMOS Process Architecture With Self Aligned Isolation and W Cladded Source/Drain”,IEEE, Transactions of 2004 International Electron Device Meeting, pp. 669-672.
C.L. Chen, et al., “High Quality Native-Oxide-Free Untrathin Oxide Grown by In-Situ HF-Vapor Treatment”,Electronic Letters, vol. 36, No. 11, (May 25, 2000), pp. 981-983.
Chung-Kuang, Huang, et al., “Two-Dimensional Numerical Simulation of Schottky Barrier MOSFET with Channel Length to 10 nn”,IEEE, pp. 842-848.
Connelly, Daniel, et al., “Optimizing Schottky S/D Offset for 25-nm Dual-Gate CMOS Performance”,IEEE Trans. Electron Devices, vol. 47 No. 5, (2003), pp. 1028-1034.
D. J. Chadi, et al., “Fermi-Level-Pinning Defects in Highly n-Doped Silicon”,Physical Review Letters, vol. 79, No. 24,NEC Research Institute, Princeton New Jersey 08540-6634, (Dec. 1997), pp. 4834-4837.
E. Yablonovitch, et al., “Unusually Low Surface-Recombination Velocity on Silicon and Germanium Surfaces”,Physical Review Letters, vol. 57, No. 2, (Jul. 14, 1986), pp. 249-252.
Elelstein, D., et al., “Full Copper Wiring in a Sub-0.25 mm CMOS ULSI Technology”,Proceedings of the IEEE International Electron Device Meeting, (Dec. 1997), pp. 773-776.
F. A. Padovani, “Forward Voltage-Current Characteristics of Metal-Silicon Schottky Barriers”,Texas Instruments, Inc., Dallas Texas, (Sep. 15, 1966), pp. 892-892.
G.B. Akers, et al., “Effects of Thermal Stability and Roughness on Electrical Properties of Tantalus Oxide Gates”,Mat. Res., Soc. Symp. Proc., vol. 567,Materials Research Society, (1999), pp. 391-395.
Gopalakrishnan, Kailash, et al., “Impact Ionization MOS (I-MOS)-Part I: Device and Circuit Simulations”,IEEE Transactions Electron Devices, vol. 52, No. 1, (2005), pp. 69-76.
Hasegawa, Hideki, et al., “Upinning of Fermi Level in Nanometer-Sized Schottky Contacts on GaAs and InP”,Reseach Center For Interface Quantum Electronics And Graduate School of Electronics And Info. Eng. Hokkaido Univ. Japan, (2000), pp. 92-96.
Heine, Vokker, “Theory of Surface States”,Physical Review Letters, vol. 138. No. 6A,Tell Telephone Lab., Murphy Jill, New Jersey, (Jun. 4, 1965).
Huang, Feng-Jung, “Metal-Oxide Semiconductor Field-Effect Transistors Using Schottky Barrier Drains”,Electronics Letters, vol. 33, No. 15, (Jul. 17, 1997), pp. 1341-1342.
I. Shalish, et al., “Yellow Luminescence And Fermi Level Pinning in GaN Layers”,American Institute of Physics, vol. 77, No. 7, (Aug. 14, 2000), pp. 987-989.
Internet, htt:p://www.rcigu.hokudai.ac.jp/RCIQEold/ReseacjAcjoeve.emts/jt, downloaded on, (Apr. 12, 2002).
Izumi, Hirot, et al., “43 Hydrogen Termination: The Ideally Finished Silicon Surface”,Ultraclean Surface Processing of Silicon Wafers: Secrets of Vlsi Manufacturinghttp://halloftechnology.com/electrical—optical/986.shtml, (Nov. 1998).
J. Hilsenbeck, et al., “Aging Behavior of Algan HFETs With Advanced Ohmic And Schottky Contacts”,Electronic letters, vol. 36, No. 11, (May 25, 2000), pp. 980-981.
J. Tersoff, “Schottky Barrier Heightsand The Continuum of Gap States”,Physical Review Letters, vol. 52, No. 6,AT&T Bell Lab., Murphy Jill, New Jersey 07974, (Feb. 6, 1984).
J.R. Patel, et al., “Arsenic Atom Location on Passive Silicon (111) Surfaces”,Physical Review B. vol. 36, No. 14, (Nov. 15, 1987), pp. 7715-7717.
K. Nauka, et al., “Surface Photovoltage Measurement of Hydrogen-Tteated Si Surfaces”,Journal of Electrochemical Society146(1), (1999),pp. 292-295.
Kamiyama, Satoshi, et al., “Ultrathin Tantalum Odise Capacitor Dielectric Layers Fabricated Using Rapid Thermal Nitridation Prior to Low Pressure Chemical Vapor Deposition”,j. Electrochem Soc., vol. 140, No. 6,The Electrochemical Society, Inc., (Jun. 6, 1993), pp. 1617.
Kedzierski, Jakub, et al., “Extension and Source/Drain Design for High-Performance FinFET Devices”,IEEE Trans. Electron Devices, vol. 50, No. 4, (Apr. 2003), pp. 952-958.
Kinura, Mitsuteru, et al., “A New Type of Schottky Tunnel Transistor”,IEEE Electron Device Letters, vol. 15, No. 10, (Oct. 1994), pp. 412-414.
L. Cai, et al., “Investigation of The Properties of Plasma-Enhanced Chemical Vapor Deposition Silicon Nitrite And its Effect on Silicon Surface Passivation”,Journal of Applied Physics, vol. 83, No. 11, (Jun. 1, 1998), pp. 5885-5889.
Lee, Takhee, et al., “Electronic Property of Metallic Nanoclusters on Semiconductor Surfaces: Implications For Nanoelectronic Device Applications”,Journal of Nanoparticle Research 2, (2000), pp. 345-362.
Louie, Steven G., et al., “Ionicity And The Theory of Schottky Barriers”,Physical Review Letters, vol. 15, No. 4,Dept. of Phys. Univ. of California, and Materials and Molecular Research Div., Lawrence Berjley Lab., Berkley, CA 94720.
M. A. Sobolewski et al., “Properties of Ultrathin Thermal Nitrides in Silicon Schottky Barrier Structures”,Applied Phy

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Process for fabricating a self-aligned deposited... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for fabricating a self-aligned deposited..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating a self-aligned deposited... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2735554

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.