Process for fabricating a non-volatile memory cell in a semicond

Details Process for fabricating a non-volatile memory cell in a semicond Process for fabricating a non-volatile memory cell in a semicond

1995-08-14

1997-05-27

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438308, 438289, H01L 218247, H01L 21265

Patent

active

056331860

ABSTRACT:
A process for fabricating a non-volatile memory cell (10) in a semiconductor device includes the formation of a doped region (28) in a semiconductor substrate (40) underlying a floating gate electrode (16) and separated therefrom by a tunnel dielectric layer (44). Stress induced failure of the tunnel dielectric layer (44) is avoided by laterally diffusing dopant atoms under the floating gate electrode (16) after completely fabricating both the floating gate electrode (16) and the underlying tunnel dielectric layer (44).

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patent: 4558509 (1985-12-01), Tiwari
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"Process and Device Technologies for 16 Mbit EPROMs With Large-Tilt-Angle Implanted P-Pocket Cell" Yoichi Ohshima, et al., Semiconductor Device Eng. Lab. Toshiba Corp. 1990 IEEE pp. 95-98, month unknown.

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