Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal
Reexamination Certificate
2002-09-05
2004-10-26
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
C438S050000, C438S053000
Reexamination Certificate
active
06808952
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to surface micromachining, and in particular to a process for fabricating a microelectromechanical (MEM) structure on a substrate from at least five and generally six or more layers of polysilicon.
BACKGROUND OF THE INVENTION
Surface micromachining, which is based on conventional integrated circuit (IC) processing technology, can be used to fabricate many different types of microelectromechanical (MEM) device structures on a substrate including accelerometers, micromotors, gear trains, moveable stages, tiltable micromirrors, etc. With each added level of polycrystalline silicon (also termed polysilicon) that can be deposited and patterned to build up the MEM structure, additional design information or complexity can be built into the MEM structure. Additionally, multiple levels of polysilicon can be connected together vertically to provide a greater out-of-plane rigidity for the MEM structure. The use of multiple connected levels of polysilicon can also produce electrostatic actuators having a larger output force.
A current limitation in the number of layers of polysilicon that can be used to form a MEM structure arises from accumulated stress in the polysilicon and a sacrificial material disposed between the polysilicon layers during construction of the device. Annealing at an elevated temperature helps to reduce the stress in the various polysilicon layers but does not substantially reduce the stress in certain types of sacrificial material (e.g. SiO
2
). As a result, the accumulated stress generally limits MEM device structures to about three or four layers of polysilicon depending upon the thickness of the sacrificial material between the polysilicon layers. With a deviation from a standard processing schedule, it has been possible to fabricate MEM device structures having five layers of polysilicon (see e.g. U.S. Pat. No. 6,082,208 to Rodgers et al, which is incorporated herein by reference). However, it has not been possible heretofore to fabricate a MEM device structure having six layers (also termed levels) of polysilicon due to the presence of the accumulated stress which becomes excessive and bows the substrate to such an extent that photolithography cannot be performed.
The present invention solves the problem of accumulated stress in a surface micromachined structure having at least five and generally six or more layers of polysilicon by providing one or more stress-compensation layers on the opposite side of the substrate to balance out the accumulated stress and thereby reduce bowing of the substrate to a level that allows further processing to complete the buildup of a particular MEM structure.
SUMMARY OF THE INVENTION
The present invention relates to a process for fabricating a microelectro-mechanical (MEM) structure on a device side of a substrate. Fabrication of the MEM structure is performed by partially building up the MEM structure by depositing and patterning a plurality of layers of polysilicon on the device side of the substrate with each adjacent pair of polysilicon layers being separated by a layer of a sacrificial material. An accumulated stress in the layers of polysilicon and the sacrificial material, even after one or more annealing steps performed during buildup of the MEM structure, is of sufficient magnitude to produce a bowing of the substrate, with the initially planar substrate being bowed with a radius of curvature that is less than a critical value which is generally in the range of 10-20 meters. This radius of curvature can prevent further buildup of the MEM structure due to limitations imposed by certain semiconductor processing tools (e.g. photolithographic projection steppers, vacuum chucks, vacuum wands, etc.). To reduce the bowing of the substrate and to increase the radius of curvature above the critical value, a stress-compensation layer is deposited on a backside of the substrate opposite the device side. Then, at least one additional layer of polysilicon can be deposited and patterned on the device side of the substrate to complete the build-up of the MEM structure. The process of the present invention can further include a step for removing the sacrificial material by selective etching to release the MEM structure for movement. This removal step (termed herein an etch release step) can performed during fabrication of the MEM structure, or at a later time (e.g. by a customer or end-user when the MEM structure is fabricated by a foundry). The step for removing the sacrificial material can also remove the stress-compensation layer partially or entirely.
The sacrificial material preferably comprises silicon dioxide or a silicate glass; and the stress-compensation layer comprises silicon dioxide or the sacrificial material. The process of the present invention can be used to form MEM structures having up to six or more layers of polysilicon, including a layer of polysilicon which is patterned to form electrical wiring to the MEM structure.
In building up the MEM structure, chemical-mechanical polishing (CMP) can be used to planarize one or more layers of the sacrificial material. To reduce a print-through of features from one patterned polysilicon layer to an overlying polysilicon layer due to a spatially varying stress in an intervening layer of the sacrificial material, the annealing step can be performed prior to planarizing the layer of the sacrificial material by CMP
Patterning of each polysilicon layer can be performed by masking and etching the polysilicon layer. Alternately, an underlying layer of the sacrificial material can be masked and etched to form a mold wherein a subsequent polysilicon layer can be deposited to define features of the MEM structure being built up on the substrate. The radius of curvature of the device side of the substrate can be determined by reflecting a light beam off the device side of the substrate.
The present invention further relates to a process for fabricating a MEM structure on a device side of a substrate, comprising steps for partially building up the MEM structure by depositing and patterning a plurality of alternating layers of polysilicon and a sacrificial material; measuring a radius of curvature of the substrate by reflecting a light beam off the device side of the substrate, with the radius of curvature being due to a bowing of the substrate that arises from an accumulated stress in the layers of polysilicon and the sacrificial material which cannot be completely eliminated by a step for annealing the substrate; depositing a stress-compensation layer on a backside of the substrate opposite the device side when the measured radius of curvature is less than a critical value; and repeating steps (a)-(c) at least one more time to complete the buildup of the MEM structure. This process can further include steps for removing the sacrificial material to release the MEM structure for movement, and removing at least one stress-compensation layer from the backside of the substrate. The MEM structure formed according to the present invention can comprise six or more layers of polysilicon, with elements of the MEM structure being formed from the various layers of polysilicon.
As described previously, the sacrificial material can comprise silicon dioxide or a silicate glass; and the stress-compensation layer can comprise silicon dioxide or the sacrificial material. The critical value for the radius of curvature is generally in the range of 10-20 meters, and can be arbitrarily selected or determined by a particular semiconductor processing tool. The above process can further include a step for planarizing at least one layer of the sacrificial material by chemical-mechanical polishing, with the annealing step preferably being performed prior to the planarizing step to reduce a print-through of features from an underlying polysilicon layer.
The present invention also relates to a process for fabricating a MEM structure on a device side of a substrate, comprising steps for depositing and patterning a plurality of alternating layers of p
Habermehl Scott D.
Hetherington Dale L.
Krygowski Thomas W.
Mani Seethambal S.
Resnick Paul J.
Hohimer John P.
Sandia Corporation
Tsai H. Jey
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