Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-04-26
2004-09-21
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S620000, C438S622000, C438S624000, C438S626000, C438S629000, C438S633000
Reexamination Certificate
active
06794286
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to techniques of buried wiring in semiconductor technology.
2. Description of the Related Art
With higher operation speed and higher integration density, wiring has become thinner and more multilayered. Since thinning of wiring results in an increase in resistance and a decrease in reliability, it is required to use low-resistance, high-reliability wiring materials such as Au, Ag, and Cu.
Such materials, however, have problems with respect to adhesion to an interlayer insulating film, diffusion into the interlayer insulating film, oxidation and agglomeration, as compared to conventional Al-based materials.
In order to solve these problems, when this kind of material is used, the periphery of wiring is coated with a film of a material different from the material of the wiring. This kind of wiring is formed, for example, by a process illustrated in
FIGS. 1A
to
1
D.
As is shown in
FIG. 1A
, at first, a semiconductor substrate
201
, on the surface of which an interlayer insulating film
202
is formed, is prepared. A barrier metal layer
203
, having effects in preventing diffusion of material wiring and enhancing adhesion, is formed on the interlayer insulating film
202
by means of vapor deposition or sputtering. A conductor
204
, which will become wiring, is formed on the barrier metal layer
203
. A barrier metal layer
205
having the same effects as the barrier metal layer
203
is formed on the conductor film
204
. A resist is coated on the barrier metal layer
205
, exposed, and developed, thereby forming a resist pattern
206
for forming wiring.
Then, as shown in
FIG. 1B
, with the resist pattern
206
used as a mask, the barrier metal layer
205
, conductor film
204
and barrier metal layer
203
are etched in a shape of wiring.
Subsequently, as shown in
FIG. 1C
, a barrier metal layer
207
, which is different from the wiring
204
and has the same effects as the barrier metal layer
203
, is formed on the entire resultant structure, thereby covering side walls of the wiring portion.
Lastly, as shown in
FIG. 1D
, the barrier metal layer
207
is anisotropically etched, thereby selectively leaving the barrier metal layer
207
on the side walls of the wiring portion.
According to this process, since the wiring structure wherein the outer surfaces of the conductor film
204
or wiring body is coated with barrier metal layers
203
,
205
and
207
is obtained, oxidation and diffusion of the wiring material can be prevented.
This process, however, has the following problems: the number of steps is large, and the insulating film provided on the wiring must be flattened, and thus this process is not suitable for multilayer structure.
If the wiring portion obtained in the step shown in
FIG. 1B
is formed in a tapered shape, the barrier metal layer
207
may not be formed on the side walls of the wiring portion, as shown in
FIG. 2A
, or the conductor film
207
on the side walls of the wiring portion may be etched at the time of the anisotropic etching, as shown in
FIG. 2B
, and, as a result, the side walls of the wiring portion are not coated with the barrier metal layer
207
. Thus, the oxidation and diffusion of the wiring material cannot be prevented.
FIGS. 3A and 3B
are cross-sectional views showing steps of another conventional wiring forming process.
At first, as shown in
FIG. 3A
, wiring
208
made of an alloy of a wiring material and a material tending to be oxidized or nitrided more easily than the wiring material is formed on a semiconductor substrate
201
on which an interlayer insulating film
202
is provided.
Then, the structure shown in
FIG. 3A
is annealed in an atmosphere including a slight quantity of oxygen or nitrogen. As a result, as shown in
FIG. 3B
, the above-mentioned material tending to be oxidized or nitrided more easily is diffused to the surfaces of the wiring
208
, and an oxide film or a nitride film
209
is formed on the entire periphery of the wiring
208
. Since the oxide film or nitride film
209
is formed, the impurity concentration in the wiring
208
decreases and the interior of the wiring
208
has properties similar to a pure metal.
This process, however, has the following problems. High-temperature heat treatment is required to form the oxide film or nitride film
209
. Because of this, transistor characteristics are adversely effected. For example, the depth of a junction increases. Moreover, since an intergranular diffusion is dominant with respect to the diffusion, it is difficult to coat the wiring
208
uniformly with the oxide film or nitride film
209
. These problems lead to degradation in reliability.
FIGS. 4A
to
4
D are cross-sectional views showing steps of another conventional wiring forming process.
As is shown in
FIG. 4A
, an interlayer insulating film
202
having a wiring groove in a surface portion thereof is formed on a semiconductor substrate
201
.
A diffusion prevention layer
210
is formed on the entire structure, as shown in
FIG. 4B
, thereby to prevent a wiring material from diffusing into the interlayer insulating film
202
. Subsequently, a conductor layer
211
which will become a buried wiring portion is formed on the entire structure. The material of the diffusion prevention film
210
is, for example, a material tending to be oxidized or nitrided more easily than the wiring material.
Then, as shown in
FIG. 4C
, the entire surface of the resultant structure is etched so as to leave the conductor film
211
only in the wiring groove, thus forming the buried wiring portion
211
.
Lastly, as shown in
FIG. 4D
, the resultant structure is annealed in an atmosphere including a slight amount of oxygen or nitrogen, and diffusion is effected in a region from the diffusion prevention film
210
up to the surface of the buried wiring portion
211
. Thus, an oxide film or nitride film
212
is formed in a surface portion of the buried wiring
211
.
According to this method, since the surface of the wiring
211
can be coated with the oxide film or nitride film
212
in a self-alignment manner, the number of steps is not increased.
However, since the intergranular diffusion is dominant with respect to the diffusion, the oxide film or nitride film
212
is not formed uniformly although the conductor film
211
is not alloyed. Therefore, there is a problem in reliability.
In addition, like the process illustrated in
FIGS. 3A and 3B
, high-temperature heat treatment is required to form the oxide film or nitride film
212
. The high-temperature heat treatment adversely affects transistor characteristics and requires completeness of the diffusion prevention film
210
.
Furthermore, since the width of the wiring
211
is decreased by the degree corresponding to the presence of the diffusion prevention film
210
, the wiring resistance increases. If the width of the wiring groove is enlarged, the problem of wiring resistance does not occur. However, because of the increase in width of the wiring groove, the wiring cannot be thinned effectively.
FIGS. 5A
to
5
D are cross-sectional views showing steps of a process for forming a through-hole in buried wiring. A wiring groove and a through-hole are formed in this order. In this invention, “through-hole” refers to a via hole for connection between wiring layers or a contact hole for connection between a wiring layer and a semiconductor substrate.
At first, as shown in
FIG. 5A
, a first interlayer insulating film
221
and a second interlayer insulating film
222
are formed on the semiconductor substrate
220
in this order. Then, a wiring groove
223
is formed in the second interlayer insulating film
222
.
Subsequently, as shown in
FIG. 5B
, a resist pattern
224
for forming the through-hole is provided. In this case, the resist pattern
224
is displaced to the right owing to misalignment.
With the resist pattern
224
used as a mask, the first interlayer insulating film
221
is etched to form a through-hole
225
, as shown in FIG.
5
C.
Since the resist pa
Aoyama Hisako
Aoyama Tomonori
Hayashi Hisataka
Iijima Tadashi
Minamihaba Gaku
Fourson George
Kabushiki Kaisha Toshiba
Maldonado Julio J.
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