Process for fabricating a metal-metal capacitor within an integr

Details Process for fabricating a metal-metal capacitor within an integr Process for fabricating a metal-metal capacitor within an integr

1998-07-17

2000-10-24

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438250, 438386, 438393, 257301, H01L 218242, H01L 2120, H01L 27108

Patent

active

061366404

ABSTRACT:
A process for fabricating a metal-metal capacitor within an integrated circuit comprises the steps of: producing a first metal electrode, a second metal electrode, and a dielectric layer on top of a lower insulating layer; and depositing an upper insulating layer on top of the two metal electrodes and the dielectric layer. The integrated circuit comprises the lower insulating layer, a first metal layer which is on top of the lower insulating layer, and the upper insulating layer which is on top of the first metal layer. The capacitor comprises the first metal electrode, the second metal electrode, and the dielectric layer wherein each of the two metal electrodes is in contact with one side of the dielectric layer. The electrodes and the dielectric layer lie between the lower insulating layer, which supports a level of metallization (M1), and the upper insulating layer which covers this level of metallization.

REFERENCES:
patent: 5789303 (1998-08-01), Leung et al.
patent: 5918135 (1999-06-01), Lee et al.
patent: 6008083 (1999-12-01), Brabazon et al.

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