Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-02-22
2001-07-03
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S581000, C438S258000
Reexamination Certificate
active
06255169
ABSTRACT:
FIELD OF THE INVENTION
This invention relates, in general, to non-volatile memory devices and, more particularly, to EEPROM devices and to methods for their fabrication.
BACKGROUND OF THE INVENTION
Non-volatile memory devices are both electrically erasable and programmable. Such devices retain data even after the power to the device is terminated. One particular type of non-volatile memory device is the (electrically-erasable-programmable-read-only-memory) EEPROM device. Non-volatile memory devices, such as the EEPROM, have a limited lifetime due to the endurance related stress such devices suffer each time they go through a program-erase cycle. The endurance of an EEPROM device is defined by the number of program-erase cycles that the device is capable of undergoing without a failure.
In a flash EEPROM device, programming and erasing is accomplished by transferring electrons to and from a floating-gate electrode through a thin dielectric layer, known as a tunnel-oxide layer, located between the floating-gate electrode and the underlying substrate. Typically, the electron transfer is carried out either by hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage is coupled to the floating-gate electrode by a control-gate electrode. The control-gate electrode is capacitively coupled to the floating-gate electrode, such that a voltage applied to the control-gate electrode is coupled to the floating-gate electrode. In one type of device, the control-gate electrode is a polycrystalline silicon gate electrode overlying the floating-gate electrode, and separated therefrom by a dielectric layer. In another type of device, the floating-gate electrode is a doped region in the semiconductor substrate.
The flash EEPROM device is programmed by applying a high positive voltage to the control-gate electrode, and a lower positive voltage to the drain region of the floating-gate transistor. These applied potentials transfer electrons from the substrate through the tunnel oxide layer and to the floating-gate electrode. Conversely, the EEPROM device is erased by grounding the control-gate electrode, and applying a high positive voltage to either the source or drain region of the floating-gate transistor. Under erase voltage conditions, electrons are removed from the floating-gate electrode and enter either source or drain regions in the semiconductor substrate.
Another type of EEPROM device is extensively used in programmable logic devices (PLDs). EEPROM cells used in PLDs include three transistors: a write transistor, a read transistor, and a sense transistor. In conventional EEPROM cells, the control gates of the write transistor and read transistor are connected to the same wordline. Also, in PLD EEPROM cells, the read transistor and the sense transistor are connected to the same bitline. When the read transistor is turned on, the common bitline connection permits the sense transistor to be effectively used as the storage cell of the EEPROM.
To program PLD EEPROMs, a high voltage (between 13 and 15 volts) is applied to the wordline of the EEPROM cell. A relatively high voltage (approximately 11 to 12 volts) is applied to the control gate of the write transistor, allowing voltage applied on the bitline to be transferred to the control-gate of the sense transistor. The application of such high voltage levels is a write condition that results in data being stored in the EEPROM cell.
To erase the EEPROM cell, a voltage V
cc
is applied to the wordline of the write transistor, which also causes the read transistor to turn on. Ground potential is applied to the bitline, which is connected to the drain of the read transistor, and a high voltage (between 13 to 15 volts) is applied on the control-gate. Under this bias condition, the high voltage applied to control-gate is coupled to the floating-gate of the sense transistor and the EEPROM cell is erased by the transfer of electrons through the tunnel oxide layer from the floating-gate to the substrate.
As described above, over time EEPROM devices will be written and erased repeatedly as data is stored and removed from the device. Since the EEPROM relies on charge exchange between the substrate and the floating-gate electrode, considerable stress is placed on the tunnel oxide layer underlying the floating-gate electrode. The charge-induced stress in the tunnel oxide layer can cause charge trapping sites to form within the tunnel oxide. The formation of these charge trapping sites is undesirable, because, once formed, electrical current can leak through the tunnel oxide layer from the floating-gate electrode to the substrate. When charge leaks off the floating-gate electrode, a data error occurs in the EEPROM device.
In addition to causing charge to leak from the floating-gate electrode, the accumulation of charge in the trapping sites causes the threshold voltage of the sense transistor to shift away from the originally designed threshold voltage. In an n-channel device, the accumulation of charge in the trapping sites causes the threshold voltage to shift to more negative values. Once the threshold voltage shifts away from the designed value, the sense transistor cannot be turned off by application of a typical read voltage applied to the floating-gate electrode. When this happens, a read error occurs and an incorrect logic signal is transmitted from the EEPROM memory cell.
Both charge leakage and threshold voltage instability produce data errors during operation of the EEPROM device. Depending upon the particular function performed by the EEPROM device, the data error can cause catastrophic failure in an electronic system relying upon the EEPROM device. Accordingly, an improved EEPROM device is necessary to provide a high-endurance EEPROM device that exhibits stable threshold voltage values.
SUMMARY OF THE INVENTION
In practicing the present invention there is provided a process for fabricating a non-volatile memory device in which a tunnel oxide layer is provided that exhibits improved resistance to stress induced current leakage. An improved tunnel oxide layer is obtained by implanting nitrogen atoms into the substrate region upon which the tunnel oxide layer is to be formed. The nitrogen-implanted substrate surface is then subjected to a thermal oxidation process to grow a thin tunnel oxide layer. During the thermal oxidation process, nitrogen is incorporated into the growing oxide layer. The nitrogenated tunnel oxide shows substantially reduced leakage currents as compared with prior art tunnel oxide layers for a given applied gate voltage. Additionally, the nitrogen implant into the substrate surface slows the oxidation rate, such that for a given set of oxidation conditions, a tunnel oxide layer having a reduced thickness is obtained. The fabrication of tunnel oxide layers having reduced thickness and increased resistance to stress induced current leakage is advantageous in the production of non-volatile memory devices. Improved programming and erasing endurance is obtained in non-volatile memory devices, such as PLD EEPROM devices, having very thin tunnel oxide layers.
In one form, a process for fabricating a non-volatile memory device includes providing a semiconductor substrate having a tunnel oxide region, and introducing nitrogen atoms into the tunnel oxide region. A tunnel oxide layer is then formed overlying the tunnel oxide region. The substrate is annealed to form a nitrogenated tunnel oxide layer, and a floating-gate electrode is formed overlying the nitrogenated tunnel oxide layer.
REFERENCES:
patent: 5610084 (1997-03-01), Solo de Zaldivar
patent: 5908312 (1999-06-01), Cheung et al.
patent: 5942780 (1999-08-01), Barsan et al.
patent: 5960274 (1999-09-01), Mehta
patent: 6017792 (2000-01-01), Sharma et al.
patent: 6069041 (2000-05-01), Tanigami et al.
Li Xiao-Yu
Mehta Sunil D.
Xiang Qi
Advanced Micro Devices , Inc.
Booth Richard
Brinks Hofer Gilson & Lione
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