Process for fabricating a flash memory device

Details Process for fabricating a flash memory device Process for fabricating a flash memory device

1998-03-18

2001-06-19

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S279000

Reexamination Certificate

active

06248629

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor devices and process for fabricating the same and, particularly to a process for fabricating a flash EPROM or EEPROM memory device.
2. Description of the Related Art
Non-volatile memory devices, and particularly so-called “flash” memory devices, have become increasingly more popular in data storage applications. The term EPROM is an acronym for Erasable Programmable Read Only Memory, while EEPROM refers to Electrically Erasable PROMs. The term “flash” in conjunction with electrical erasable programmable read only memory or “flash EEPROMS”, generally refers to EEPROM memory cells which are programmed by hot electron injection and erased by Fowler-Nordheim tunneling. The operation and structure of such devices is discussed in U.S. Pat. No. 4,698,787, issued Oct. 6, 1987, to Mukherjee et al., and IEEE Journal of Solid State Circuitry, Vol. SC-22, No. 5, October, 1987, pages 676-683 in an article entitled, “A 128K Flash EEPROM Using Double Polysilicon Technology” by Gheorghe Samachisa, et al.
Generally, an array of flash EPROM or EEPROM memory cells may be formed on a semiconductor substrate in a series of rows and columns, accessed by conductors referred to as word lines and bit lines. A portion of an array is illustrated schematically in FIG.
1
A. In
FIG. 1A
, a two-by-two matrix of memory cells
100
is shown with a first memory cell
20
having its drain connected to bit line
0
(BL
0
), its control gate coupled to word line
0
(WL
0
) and its source floating. Also shown in
FIG. 1A
is a second memory cell
22
also having its drain connected to BL
0
, its control gate coupled to word line
1
(WL
1
) and its source floating. As illustrated in
FIG. 1A
, the sources of the memory cells
20
,
22
,
24
and
26
are shown to be floating; however, the sources can be connected to form a common source line.
To program a cell, such as cell
20
, the hot injection mechanism is normally induced by grounding the source region, applying a relatively high positive voltage (approximately 12V) to the control gate and applying a moderate voltage (approximately 5V or V
cc
) to the drain in order to generate high energy (hot) electrons. After sufficient negative charge accumulates onto the floating gate, the negative potential of the floating gate rises to a threshold voltage and inhibits current flow through the channel region during any subsequent read mode operation. Typically, in the read mode, a relatively low positive voltage, for example 1.5V, is applied to the drain, 5V or V
cc
is applied to the control gate and 0V is applied to the source of the memory cell. The magnitude of the read current is used in determining whether the flash EPROM or EEPROM cell is programmed or not.
Erasing flash EPROM or EEPROM cells is typically carried out by Fowler-Nordheim tunneling between the floating gate and the source (known as source erase or negative gate erase) or between the floating gate and the substrate (known as channel erase). The source erase operation is induced by applying a high positive voltage (approximately 12V) to the source region and 0V to both the control gate and the substrate, while floating the drain region of the memory cell. The negative gate erase operation is induced by applying 5V or V
cc
to the source region, and negative voltage (as much as −10V) to the control gate and 0V to the substrate, while floating the drain of the memory cell. The channel erase operation is induced by applying a high positive voltage (approximately 12V) to the substrate and 0V to the control gate, while floating both the source and drain of the memory cell.
As shown in
FIG. 1B
, in a memory device such as a flash EPROM or EEPROM, memory cells are arranged in a common region, with the memory cell region (a portion of which is shown in
FIG. 1A
) of the flash memory array being referred to as the “core” area of the chip. All other devices necessary for operation of the device, such as the select transistors and amplifiers, are located in the “periphery” area of the chip. In the core region, all memory cells have essentially the same dimensions, allowing simultaneous fabrication of the cells in the core region using common processing steps. Each memory cell is formed in the semiconductor substrate by, for example, diffusion of an n+ drain region, and an n type, double diffused source region, with a channel region positioned between the drain and source regions. The double diffused source region is formed of a deeply diffused, but lightly doped n type region, commonly doped with phosphorous (known as a double diffused junction (DDJ)), and a more heavily doped but more shallowly diffused n+ region, commonly doped with arsenic (As) within the DDJ. A tunnel oxide is formed on the silicon substrate separating a floating gate from the source and drain regions, and a control gate is formed over the floating gate, separated therefrom by an inter-polysilicon dielectric layer.
FIG. 2
illustrates a top view of a portion of a semiconductor substrate under fabrication as a flash cell, such as that shown schematically in FIG.
1
A. Shown in
FIG. 2
are two unit cells
20
,
22
, formed by a second polysilicon gate layer or control gate layer
32
(defining wordline ø (WLø)) deposited on top of an interdielectric layer
30
(shown in
FIG. 5
) such as oxinitride, and a first polysilicon gate layer or floating gate layer
29
. Field oxide regions
42
formed by, for example, a LOCOS process, separate and isolates adjacent memory devices. A common source region
43
is used for adjacent cells and is formed by a self-aligned source mask and etch, as discussed below.
One conventional method of manufacturing a flash EPROM or EEPROM array includes a number of separate masking steps between the point in time when polysilicon layers (or “poly stack”) which will form control gate and floating gate regions are deposited onto a substrate, and the steps of formation of the core memory devices. (It should be recognized that complete processing of the integrated circuit requires a substantial number of processing steps which are not detailed here in order not to unduly obscure the nature of the present invention. Such processing steps would be within the knowledge and skill of one of average skill in the art.)
In general, in one exemplary prior art process, the periphery devices are formed early in the process sequence, with the core region covered by a mask layer to prevent processing occurring in the periphery area from affecting the core area. After the periphery devices are formed, the masking over the core area is removed and the core area cells are formed, followed by junction implantation processing in the periphery area. The conventional process for forming the periphery cells requires the use of several masks to protect the core memory area from damage during its formation.
One portion of a conventional process flow which may be used for forming a memory array is illustrated in
FIGS. 3-8
. In
FIGS. 3-8
, the left side of each figure represents cross-sections of the core area (
10
), while the right side of each figure represents cross-sections of process steps occurring in the periphery area (
12
).
FIGS. 7A and 7B
illustrate the effects of identical process steps on different cross-sections of the device, represented along line A—A and B—B, respectively, in FIG.
2
.
FIG. 3
shows a wafer substrate
50
having formed on it lateral isolation by, for example, a local oxidation of silicon (LOCOS) process growing select portions of a pad oxide resulting in field oxide regions
42
1
-
42
2
(
FIG. 2
) and
42
3
-
42
4
(FIG.
3
). After formation of the field oxide regions, conventional polysilicon layer deposition and masking techniques will result in the provision of a first polysilicon layer
29
and an inter-polysilicon dielectric layer
30
, overlying core region
10
of the array. A second polysilicon layer
32
is simultaneously deposited in both core region
10
and periphery region

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