Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-02-27
2003-09-23
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S229000, C438S231000
Reexamination Certificate
active
06624014
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for semiconductor devices. More specifically, it relates to a process for fabricating a deep submicron complementary metal oxide semiconductor device having ultra shallow junctions.
2. Description of the Related Art
The design of a lightly doped drain is widely used to reduce the short channel effects generated in NMOS and CMOS devices. It is achieved by further providing a source/drain region near the channel having less dopants than the original MOS source/drain region.
By increasing the integration of the integrated circuit, the area of the semiconductor device is decreased and the design dimension is thus reduced. Due to the advances in the semiconductor technology, the integration of integrated circuit devices have been developed to deep submicron. In deep submicron complementary metal oxide semiconductor devices, the doping is carried out with an implanting energy of only thousand eV, called a shallow junction process. An ultra shallow junction is formed for the lightly doped drain to prevent the short channel effect.
However, in a conventional shallow junction process the diffusion of the boron ions is larger than that of the arsenic ions. Therefore, by using the conventional implantation process it is difficult to form P+/N type and N+/P type ultra shallow junctions, since the semiconductor processes have been reduced to a level lower than 0.18 micron.
In order to overcome the prior problems, a Ge morphize preimplantation is usually adopted.
FIGS. 1A
to
1
F are cross sectional views showing a conventional process for fabricating shallow junctions of a complementary metal oxide semiconductor device. First, with reference to
FIG. 1A
, an N well region
102
and a P well region
104
are formed on the substrate
100
, separated from each other by a shallow trench isolation
106
. Then, a polysilicon gate
108
is formed on the N well region
102
and the P well region
104
, respectively. A Ge premorphize implantation
110
is carried out on the surface of the above structure to form amorphous silicon regions
112
and
114
on the N well region
102
and P well region
104
, respectively. The energy for implantation is in the range of about 2000 to 5000 eV.
Referring to
FIG. 1B
, a photoresist layer
116
is formed on the P well region
104
. A P type ion implantation
118
using boron ions is performed in the N well region
102
so that the amorphous silicon region
112
on the surface of the N well region
102
adsorbs the P type ions. The energy for implantation is lower than 1000 eV.
Referring to
FIG. 1C
, (it doesn't show that the photoresist layer is removed) after the photoresist layer
116
is removed, another photoresist layer
122
is formed on the N well region
102
. An N type ion implantation
124
using arsenic ions is carried out on the surface of the P well region
104
so that the amorphous silicon region
114
on the surface of the P well region
104
adsorbs the N type ions. The energy for implantation is no more than about 2000 eV.
Referring to
FIG. 1D
, (it doesn't state that the photoresist layer is removed) after the photoresist layer
122
is removed, spacers
128
are formed on the sidewalls of the polysilicon gate
108
by deposition and etching back.
Referring to
FIG. 1E
, P type and N type ions are heavily implanted into the N well region
102
and the P well region
104
, respectively. Finally, a rapid thermal process is performed to form source/drain regions
130
,
132
and shallow junctions
120
,
126
on the complementary metal oxide semiconductor device.
In the above process for fabricating a complementary metal oxide semiconductor, in order to eliminate the channel effect resulted from ion implantation, a Ge premorphize implantation is carried out, before implanting dopants, to form a amorphous silicon layer on the crystalline substrate, thereby controlling the depth of the junction. However, such approach has some problems such as the existence of some voids at the interface of the amorphous silicon layer and the surface of the substrate/crystalline substrate. Furthermore, such Ge premorphize implantation process may result in damage on the surface of the silicon substrate.
In a conventional process, in order to decrease the depth of the junction, the energy for ion implantation has to be reduced. However, the ejecting range of the dopant is reduced as the energy for ion implantation is decreased. For low energy (no more than thousands eV) boron ion implantation, the depth of the junction would not be significantly decreased by lowering the energy of the ion implantation. Moreover, the boron dopants bond the voids in the silicon substrate to form a boron-void combination which results in transient enhanced diffusion (TED). In the course of annealing, such boron-void combination diffuses very rapidly and has a deeper junction than that obtained by boron alone. An oxygen enhanced diffusion (OED) effect allows the oxygen atoms to diffuse into the silicon substrate when annealing. Even if the boron ions are implanted with the energy lower than thousands eV, the transient enhanced diffusion and the oxygen enhanced diffusion still exist. Further, it is difficult to apply the existing ion implantation equipment used in the boron ion implantation with a voltage of no more than thousands eV. Therefore, it is required that the ion implantation device is replaced although no device useful in mass production is available.
SUMMARY OF THE INVENTION
To overcome the disadvantages set forth above, it is one object of the present invention to provide a process far fabricating a complementary metal oxide semiconductor device having ultra shallow metal junctions. A low-stressed silicon nitride layer is formed to adsorb ions as a diffusion source layer when light ion implantation is performed. The silicon nitride layer is also used to prevent damage on the surface of the silicon substrate during the Ge preamorphizing implantation and furthermore to prevent the channel effect resulting from ion implantation. Therefore, the process of the present invention is suitable for deep submicron technology to produce a device having a smaller size and a higher reliability.
Another object of the present invention is to form ultra shallow junctions having an ultra small depth and a low resistance in order to reduce the short channel effect, and thereby reducing the transient enhanced diffusion and oxygen enhanced effect.
Furthermore another object of the present invention is to provide a process for forming ultra shallow junctions which can perform ion implantation by using the existing device and which can be applied in a process lower than 0.1 &mgr;m.
According to one aspect of the present invention, a process for fabricating a complementary metal oxide semiconductor device is provided. After a gate is formed on the substrate on which a N well region and a P well region are separated from each other by a shallow trench isolation, a diffusion source layer having a thickness of about 200 to 400 angstrom is formed. Subsequently, a photoresist layer is formed on the P well region. A light ion implantation is performed in the N well region by using P type ions with a concentration ranged from 10
14
to 10
15
/cm
2
with an energy level of 1 to 15 Kev. A P type diffusion source layer is formed on the N well region. After the photoresist layer covering the P well region is removed, another photoresist layer is covered on the N well region. A light ion implantation is performed on the P well region by using N type ions with a concentration ranged from 10
14
to 10
15
/cm
2
by using an energy level of 1 to 10 Kev to form a N type diffusion source layer in the P well region. After the photoresist layer on the N well region is removed, spacers are formed on the sidewalls of the gate by deposition and etching back. Then, a heavy implantation of P type and N type are performed in the N well region and the P wellregion, respectively to form the source/dr
J.C. Patents
Pert Evan
United Microelectronics Corp.
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